An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels.

An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.

A semiconductor device includes a semiconductor substrate having a predetermined region in which a standard cell is disposed, and also includes: a first circuit connected to a first ground power line; a second circuit that is connected to a second ground power line and formed from the standard cells; and a protection circuit interposed and connected between the first circuit and the second circuit. The protection circuit includes: a resistor connected in series between the first circuit and the second circuit; and a protector that is interposed and connected between a node of the resistor on the second circuit side and the second ground power line and clamps a potential difference between the node and the second ground power line to a predetermined voltage or lower. The protection circuit is formed in a protection cell disposed in the predetermined region.

A structure for preventing charge induced leakage of a semiconductor device includes a shield separated from a first interconnect by at least a first lateral spacing and separated from a second interconnect by at least a second lateral spacing. The first interconnect is connected to a first junction and the second interconnect is connected to a second junction. A shield bias is connected to the shield to terminate an electromagnetic field on the shield. The shield between the first and second lateral spacings has a minimum width to substantially prevent formation of a conductive channel between the first and second junctions. The shield may be formed over a portion of the first junction and over a portion of the second junction to substantially prevent formation of another conductive channel between the first and second junctions at a location that does not have the first and second lateral spacings.

Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.

A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of via opens, and the second DOE contains fill cells configured to enable NC detection of stitch opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.