A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source/drain (S/D) regions on the first and second fin structures, respectively, forming first and second oxidation stop layers on the n- and p-type S/D regions, respectively, epitaxially growing first and second semiconductor layers on the first and second oxidation stop layers, respectively, converting the first and second semiconductor layers into first and second semiconductor oxide layers, respectively, forming a first silicide-germanide layer on the p-type S/D region, and forming a second silicide-germanide layer on the first silicide-germanide layer and on the n-type S/D region.

An organometallic compound is represented by Formula 1. A light-emitting device includes a first electrode, a second electrode facing the first electrode, an interlayer disposed between the first electrode and the second electrode and including an emission layer, and at least one organometallic compound represented by Formula 1. An electronic apparatus includes the light-emitting device.

A pixel includes a light emitting element including an anode and a cathode, a first transistor connected between the anode and a first power line and switched by a voltage of a node, a second transistor connected between the first transistor connected to the first power line and a data line and switched by a write scan signal, a third transistor connected between the node and the anode and switched by a compensation scan signal, and an insulating layer covering the second and third transistors. A first groove is defined in a portion of the insulating layer adjacent to the third transistor.

A display device includes a circuit element layer including at least one transistor, a display element layer disposed on the circuit element layer and including a first area including first, second, and third light emitting areas and a first non-light-emitting area and a second area including fourth, fifth, and sixth areas and a second non-light-emitting area, a first light emitting element to provide a first light to each of the first light emitting area and the fourth light emitting area, a second light emitting element to provide a second light to each of the second light emitting area and the fifth emitting area, and a third light emitting element to provide a third light to each of the third light emitting area and the sixth emitting area, a pixel definition layer provided with openings, and a division pattern disposed in at least some of the openings. The division pattern divides each of the fourth, fifth, and sixth light emitting areas of the second area into a plurality of sub-unit areas. The second non-light-emitting area of the second area includes a first sub-non-light-emitting area and a second sub-non-light-emitting area, and the pixel definition layer overlaps the first non-light-emitting area of the first area and the first sub-non-light-emitting area of the second area and has a transmittance different from a transmittance of the division pattern.

A display panel includes light-emitting electrodes respectively disposed in first to third emission areas, first intermediate layers respectively disposed in the first to third emission areas and respectively overlapping the light-emitting electrodes, a bank layer covering an edge of each of the first intermediate layers and including openings respectively overlapping the first intermediate layers, a counter electrode disposed on the bank layer and covering the light-emitting electrodes, quantum dot light-emitting layers arranged below the counter electrode and respectively disposed in the first to third emission areas, and a second intermediate layer between the first intermediate layer in the first emission area and the quantum dot light-emitting layer in the first emission area. The second intermediate layer is disposed in an opening of the bank layer corresponding to the first emission area, the opening being one of the openings of the bank layer.

An organic electroluminescence device comprising: a cathode; an anode; an emitting layer disposed between the cathode and the anode; and a first layer disposed between the emitting layer and the cathode, wherein the emitting layer comprises a host compound, the first layer comprises a first compound and a second compound, and the three compounds are in a relationship satisfying the following Conditions 1 and 2: (Condition 1) the electron affinity Af.sub.H of the host compound and the electron affinity Af.sub.ETA of the first compound satisfy the following expressions (1-1) and (1-2):

Af.sub.H<Af.sub.ETA  (1-1)

|Af.sub.H−Af.sub.ETA|≤0.10  (1-2) (Condition 2) the electron affinity Af.sub.H of the host compound and the electron affinity Af.sub.ETB of the second compound satisfy the following expressions (2-1) and (2-2):

Af.sub.H>Af.sub.ETB  (2-1)

|A.sub.fH−Af.sub.ETB|≤0.10  (2-2).

A display device includes a substrate, an emission structure disposed on the substrate, a first refraction pattern disposed on the emission structure, a second refraction pattern disposed on the first refraction pattern and covering the first refraction pattern, where the second refraction pattern includes an inorganic material, and a third refraction pattern disposed on the second refraction pattern and having a refractive index less than a refractive index of the first refraction pattern.

A nonvolatile memory device is provided. The device comprises an active region, a floating gate over the active region and a wordline next to the floating gate. The floating gate has at least two narrow tips adjacent to the wordline and a portion of the floating gate between the narrow tips has a concave profile.

The structure and technology to improve the device performance of III-nitride semiconductor transistors at high drain voltage when the device is off is disclosed. P-type semiconductor regions are disposed between the gate electrode and the drain contact of the transistor structure. The P-type regions are electrically connected to the drain electrode. In some embodiments, the P-type regions are physically contacting the drain contact. In other embodiments, the P-type regions are physically separate from the drain contact, but electrically connected to the drain contact.

A pixel includes a first capacitor connected between first and second nodes, a second capacitor connected between a first voltage line and the first node, a light emitting diode including a first electrode and a second electrode connected with a second voltage line, a first transistor including a first electrode, a second electrode, and a gate electrode connected with the second node, a second transistor including a first electrode, a second electrode, and a gate electrode which receives a scan signal, a third transistor including a first electrode, a second electrode, and a gate electrode which receives a first compensation scan signal, a fourth transistor including a first electrode, a second electrode, and a gate electrode which receives a second compensation scan signal, and a fifth transistor including a first electrode, a second electrode, and a gate electrode which receives a first light emitting signal.