A superconductor transistor structure includes a source electrode and a drain electrode on a same plane as the source electrode. There is a channel region on top of the source and drain electrodes and configured to carry a current. A gate structure comprising a metallic material is on top of the channel region. The source and drain are located on a side that is opposite to that of the gate structure, with respect to the channel region.

Systems, apparatus, and methods for initializing spin qubits with no external magnetic fields are described. An apparatus for quantum computing includes a quantum well and a pair of contacts. At least one of the contacts is formed of a ferromagnetic material. One of the contacts in the pair of contacts interfaces with a semiconductor material at a first position adjacent to the quantum well and the other contact in the pair of contacts interfaces with the semiconductor material at a second position adjacent to the quantum well. The ferromagnetic material initializes an electron or hole with a spin state prior to injection into the quantum well.

A quantum well device includes a first layer of a first two-dimensional material, a second layer of a second two-dimensional material, and a third layer of a third two-dimensional material disposed between the first layer and second layer. The first layer, the second layer, and the third layer are adhered predominantly by van der Waals force.

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

There is provided a quantum heterostructure and related devices, as well as methods for manufacturing the same. The quantum heterostructure includes a stack of coextending GeSn buffer layers and each GeSn buffer layer has a different Sn content one from another. The quantum heterostructure also includes a quantum well extending over the stack of coextending GeSn buffer layers, the quantum well comprising a highly tensile-strained layer, the highly tensile-strained layer comprising at least one group IV element and having a strain greater than or equal to 1%. The quantum heterostructure is compatible with silicon-based processing, manufacturing, and technologies. The method includes changing a reactor temperature and varying a molar fraction of an Sn-based precursor to achieve a stack of coextending GeSn buffer layers, each having a different Sn composition, on a substrate provided inside the reactor chamber and forming the quantum well over the stack of coextending GeSn buffer layers.

Described are Zn.sub.xCd.sub.1-xS.sub.ySe.sub.1-y/ZnS.sub.zSe.sub.1-z core/shell nanocrystals, CdTe/CdS/ZnS core/shell/shell nanocrystals, optionally doped Zn(S,Se,Te) nano- and quantum wires, and SnS quantum sheets or ribbons, methods for making the same, and their use in biomedical and photonic applications, such as sensors for analytes in cells and preparation of field effect transistors.

An electronic device is disclosed. The electronic device includes: a first electrode disposed on a substrate and extending in a first direction; a second electrode disposed above the first electrode and extending in a second direction intersecting the first direction; and at least one switching particle disposed between the first electrode and the second electrode and bonded to the first electrode and the second electrode via van der Waals bond, wherein the switching particle controls flow of current between the first electrode and the second electrode, based on a difference of voltages of the first electrode and the second electrode applied thereto.

The methods of manufacture of GeSiSn heterojunction bipolar transistors, which include light emitting transistors and transistor lasers and photo-transistors and their related structures are described herein. Other embodiments are also disclosed herein.

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.