A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.

A quantum dot including a semiconductor nanocrystal core and a semiconductor nanocrystal shell disposed on the core and does not include cadmium, wherein the core includes a Group III-V compound, the quantum dot has a maximum photoluminescence peak in a green light wavelength region, a full width at half maximum (FWHM) of the maximum photoluminescence peak is less than about 50 nanometers (nm), and a difference between a wavelength of the maximum photoluminescence peak and a first absorption peak wavelength of the quantum dot is less than or equal to about 25 nanometers, and a production method thereof.

Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

A tunneling field effect transistor according to an embodiment of the present invention includes: a first semiconductor layer having a first conductive type; a second semiconductor layer having a second conductive type and realizing a heterojunction with respect to the first semiconductor layer in a first region; a gate insulating layer over the second semiconductor layer in the first region; a gate electrode layer over the gate insulating layer; a first electrode layer electrically connected to the first semiconductor layer; a second electrode layer electrically connected to the second semiconductor layer; and a first insulating layer interposed between the first semiconductor layer and the second semiconductor layer in a second region adjacent to the first region toward the second electrode layer.

Provided are P-type semiconductor layer, P-type multilevel element, and manufacturing method for the element. The P-type multilevel element comprises a gate electrode, an active structure overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the active structure, and source and drain electrodes electrically connected to both ends of the active structure, respectively. The active structure has a first P-type active layer, a second P-type active layer, and a barrier layer disposed between the first P-type active layer and the second P-type active layer. A threshold voltage for forming a channel in the first P-type active layer and a threshold voltage for forming a channel in the second P-type active layer have different values.

Provided are an optical sensor including graphene quantum dots and an image sensor including an optical sensing layer. The optical sensor may include a graphene quantum dot layer that includes a plurality of first graphene quantum dots bonded to a first functional group and a plurality of second graphene quantum dots bonded to a second functional group that is different from the first functional group. An absorption wavelength band of the optical sensor may be adjusted based on types of functional groups bonded to the respective graphene quantum dots and/or sizes of the graphene quantum dots.

The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.