An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of Al.sub.xGa.sub.(1-x)N, Al.sub.yGa.sub.(1-y)N, and Al.sub.zGa.sub.(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

A ferroelectric memory device according to one embodiment includes a semiconductor substrate, a fin structure disposed on the semiconductor substrate and having a trench, the trench having a bottom surface and a sidewall surface; a ferroelectric layer disposed on the bottom surface and the sidewall surface of the trench; a plurality of resistor layers stacked vertically in the trench, each resistor layer of the plurality of resistor layers having a different electrical resistance; and a gate electrode layer electrically connected to the each resistor layer in the plurality of resistor layers. The plurality of resistor layers are disposed between the gate electrode layer and the ferroelectric layer.

A method for forming a superjunction power semiconductor device includes forming multiple epitaxial layers of a first conductivity type on a semiconductor substrate and implanting dopants of a second conductivity type into each epitaxial layer to form a first group of implanted regions in a first region and a second group of implanted regions in a second region in each epitaxial layer. The multiple epitaxial layers are annealed to form multiple columns of the second conductivity type having slanted sidewalls across the first to last epitaxial layers. The columns include a first group of columns formed by the implanted regions of the first group and having a first grading and a second group of columns formed by the implanted regions of the second group and having a second grading, where the second grading is less than the first grading.

One or more semiconductor structures comprising a hole draining structure are provided. A semiconductor structure has a first layer formed over a substrate. The first layer has a first concentration of a metal material. The semiconductor structure has a second layer formed over the first layer. The second layer has a second concentration of the metal material different than the first concentration of the metal material. The semiconductor structure has a hole draining structure formed from a superlattice formed between the first layer and the second layer. The hole draining structure has a concentration of the metal material increasing towards the first layer and decreasing towards the second layer.

GAAFET threshold voltages are tuned by introducing dopants into a channel region. In a GAAFET that has a stacked channel structure, dopants can be introduced into multiple channels by first doping nano-structured layers adjacent to the channels. Then, by an anneal operation, dopants can be driven, from surfaces of the doped layers into the channels, to achieve a graduated dopant concentration profile. Following the anneal operation and after the dopants are diffused into the channels, depleted doped layers can be replaced with a gate structure to provide radial control of current in the surface-doped channels.

Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28; and a superlattice between the first and second single crystal silicon layers. The superlattice may include stacked groups of layers, with each group of layers including stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.

Disclosed are a semiconductor structure and a manufacturing method therefor, solving a problem that a surface of an epitaxial layer is not easy to flatten as the epitaxial layer has a large stress. The semiconductor structure includes: a substrate; a patterned AlN/AlGaN seed layer on the substrate; and an AlGaN epitaxial layer formed on the patterned AlN/AlGaN seed layer.

A superlattice structure includes a substrate. A first superlattice stack is disposed on the substrate. The first superlattice stack includes a first superlattice layer, a second superlattice layer and a third superlattice layer disposed from bottom to top. Three stress relaxation layers respectively disposed between the first superlattice layer and the second superlattice layer, the second superlattice layer and the third superlattice layer and on the third superlattice layer. Each of the stress relaxation layers includes a group III-V compound layer. The thickness of each of the stress relaxation layers should be greater than a relaxation critical thickness.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.