A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°. The semiconductor device may further include a superlattice on the active region including stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a semiconductor circuit on the substrate including the superlattice.

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are made of materials respectively represented by chemical formulas of Al.sub.xGa.sub.(1-x)N, Al.sub.yGa.sub.(1-y)N, and Al.sub.zGa.sub.(1-z)N. For each of the p-i-n heterojunction stacks, x decreases and z increases along a direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.

The present application provides a semiconductor structure. The semiconductor structure includes a channel layer and a barrier layer provided on the channel layer. The barrier layer includes multiple barrier layers arranged in a stack, the multiple barrier sub-layers include at least three barrier sub-layers, and Al component proportions of the multiple barrier sub-layers vary along a growth direction of the barrier layer for at least one up-and-down fluctuation.

A superconducting coupling device includes a resonator structure. The resonator structure has a first end configured to be coupled to a first device and a second end configured to be coupled to a second device. The device further includes an electron system coupled to the resonator structure, and a gate positioned proximal to a portion of the electron system. The electron system and the gate are configured to interrupt the resonator structure at one or more predetermined locations forming a switch. The gate is configured to receive a gate voltage and vary an inductance of the electron system based upon the gate voltage. The varying of the inductance induces the resonator structure to vary a strength of coupling between the first device and the second device.

A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.

The present disclosure provides a semiconductor structure, including: a substrate and a heterojunction structure disposed on the substrate, where the heterojunction structure includes a source region, a drain region, and a gate region disposed between the source region and the drain region, and the drain region is provided with a quantum well structure. The quantum well structure is provided in the drain region of the heterojunction structure, and the quantum well structure is used to generate photons by recombination luminescence, the photons can be radiated not only on the surface region of the potential barrier layer but also into the interior of the heterojunction structure, thereby the release process of electrons captured by the defects can be accelerated to reduce the current collapse effect as well as the dynamic on-resistance.

An epitaxial wafer and a semiconductor memory device, the epitaxial wafer including a semiconductor substrate having a front surface and a rear surface opposite to each other; a strain relaxed buffer (SRB) layer on and entirely covering the front surface of the semiconductor substrate; and a multi-stack on and entirely covering a surface of the SRB layer, wherein the SRB layer includes a silicon germanium (SiGe) epitaxial layer including germanium (Ge) at a first concentration of about 2.5 at % to about 18 at %, and the multi-stack has a superlattice structure in which a plurality of silicon (Si) layers and a plurality of SiGe layers are alternately provided.