An integrated circuit (IC) with a semiconductor device and an interconnect structure with carbon layers and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a source/drain region on the fin structure, forming a contact structure on the S/D region, forming an oxide layer on the contact structure, forming a conductive carbon line within a first insulating carbon layer on the oxide layer, forming a second insulating carbon layer on the first insulating carbon layer, and forming a via within the second insulating carbon layer.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron is less than 1.0×10.sup.14 cm.sup.−3 at any position in the plane of the epitaxial layer.

Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side section of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal whilst the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.

Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

A semiconductor laminate includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and an epitaxial layer composed of silicon carbide disposed on the first main surface. The second main surface has an average value of roughness Ra of 0.1 μm or more and 1 μm or less with a standard deviation of 25% or less of the average value.

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

Provided is a manufacturing method for manufacturing a SiC substrate having a flattened surface, including etching the surface of the SiC substrate by irradiating the surface of the SiC substrate with atomic hydrogen while the SiC substrate having an off angle is heated. In the etching, the SiC substrate may be heated within a range of 800° C. or higher and 1200° C. or lower.

A semiconductor device, including a substrate, a deposition layer deposited on the substrate, a semiconductor region selectively provided in the deposition layer, a semiconductor layer provided on the deposition layer and the semiconductor region, a first region and a second region selectively provided in the semiconductor layer, a gate electrode provided on the second region and the semiconductor layer via a gate insulating film, a source electrode in contact with the semiconductor layer and the second region, an interlayer insulating film covering the gate electrode, a drain electrode provided on the substrate, a plating film selectively provided on the source electrode at portions thereof on which the protective film is not provided, and a pin-shaped electrode connected to the plating film via solder. The second region is not formed directly beneath a portion where the plating film, the protective film and the source electrode are in contact with one another.