A semiconductor device has a cell region, a dividing region dividing the cell region in an expanding direction of a stacking fault band, and a termination region, and includes in a dividing region, a semiconductor layer including a drift region of a first conductivity type and a second well region of a second conductivity type provided in an upper portion of the drift region, a second interlayer insulating film provided on the semiconductor layer, and a source electrode provided on the second interlayer insulating film. The second interlayer insulating film has two second contact holes aligned in an expanding direction of stacking fault band and electrically connecting the source electrode to the second well region. The second well region is formed as one region continuous in the expanding direction of stacking fault band in the region interposed between the two second contact holes in top view.

A power semiconductor device includes a base semiconductor layer including impurities of a first conductivity type; a body portion provided on the base semiconductor layer and defined by a source trench, the body portion including a gate trench extending inwardly from an upper surface of the body portion; a gate electrode provided in the gate trench; a source electrode provided on the body portion and spaced apart from the gate electrode; and a drain electrode provided below the base semiconductor layer, wherein the body portion includes: a drift layer provided on the base semiconductor layer and including impurities of the first conductivity type; and a pair of shielding regions provided in the drift layer, spaced apart from each other in a horizontal direction, and spaced apart from the base semiconductor layer and the gate trench, the pair of shielding regions including impurities of a second conductivity type different from the first conductivity type.

The present invention provides a self-healing field-effect transistor (FET) device comprising a self-healing substrate and a self-healing dielectric layer, said substrate and said layer comprising a disulfide-containing poly(urea-urethane) (PUU) polymer, wherein the dielectric layer has a thickness of less than about 10 μm, a gate electrode, at least one source electrode, and at least one drain electrode, said electrodes comprising electrically conductive elongated nanostructures; and at least one channel comprising semi-conducting elongated nanostructures. Further provided is a method for fabricating the FET device.

A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a first diamond layer are sequentially deposited on the III-Nitride layer. Next, the silicon carrier wafer and the protection layer are removed. Then, a silicon substrate wafer that includes a protection layer, silicon substrate and a diamond layer is prepared and glass bonded to the first diamond layer.

A semiconductor device includes a semiconductor layer structure of a wide band-gap semiconductor material. The semiconductor layer structure includes a drift region having a first conductivity type and a well region having a second conductivity type. A plurality of segmented gate trenches extend in a first direction in the semiconductor layer structure. The segmented gate trenches include respective gate trench segments that are spaced apart from each other in the first direction with intervening regions of the semiconductor layer structure therebetween. Related devices and fabrication methods are also discussed.

Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.

According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.

A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; a control electrode provided inside a trench of the semiconductor part; a third electrode provided inside the trench; a diode element provided at the front surface of the semiconductor part; a resistance element provided on the front surface of the semiconductor part via an insulating film, the diode element being electrically connected to the second electrode; a first interconnect electrically connecting the diode element and the resistance element, the first interconnect being electrically connected to the third electrode; and a second interconnect electrically connecting the resistance element and the semiconductor part. The resistance element is connected in series to the diode element. The diode element is provided to have a rectifying property reverse to a current direction flowing from the resistance element to the second electrode.