Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

This disclosure provides a semiconductor epitaxial structure and a semiconductor device. The semiconductor epitaxial structure includes a channel layer, a composite barrier layer, and a doping layer. The doping layer is disposed on the composite barrier layer, the channel layer is disposed on a side of the composite barrier layer that faces away from the doping layer, the composite barrier layer includes a digital alloy barrier layer and an AlGaN barrier layer that are disposed in a laminated manner, and the digital alloy barrier layer includes one or more AlN layers. The semiconductor epitaxial structure provided in this disclosure effectively prevents Mg ions in a p-GaN layer from diffusing to the barrier layer and the channel layer to affect density and mobility of two-dimensional electronic gas and cause a problem of an increase in on resistance.

A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

A manufacturing method for a semiconductor element includes a step of forming a mask partly having an opening and configured to cover a surface of a base substrate, and a step of forming a semiconductor layer containing a predetermined semiconductor material by inducing epitaxial growth along the mask from the surface of the base substrate exposed from an opening. A surface on the side closer to the semiconductor layer in the mask is formed of an amorphous first material that does not contain an element to serve as a donor or an acceptor in the predetermined semiconductor material.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer comprises a first layer, a second layer and a third layer in order from the SiC substrate side, the nitrogen concentration of the SiC substrate is 6.0×10.sup.18 cm.sup.−3 or more and 1.5×10.sup.19 cm.sup.−3 or less, the nitrogen concentration of the first layer is 1.0×10.sup.17 cm.sup.−3 or more and 1.5×10.sup.18 cm.sup.−3 or less, the nitrogen concentration of the second layer is 1.0×10.sup.18 cm.sup.−3 or more and 5.0×10.sup.18 cm.sup.−3 or less, and the nitrogen concentration of the third layer is 5.0×10.sup.13 cm.sup.−3 or more and 1.0×10.sup.17 cm.sup.−3 or less.

A semiconductor device includes a plurality of column portions including a semiconductor. The plurality of column portions each includes a source region, a drain region, and a channel formation region including a channel formed between the source region and the drain region. The semiconductor device further includes a gate electrode provided, via an insulating layer, at a side wall of the channel formation region, and also includes a first semiconductor layer provided at a side wall of the drain region. A conductive type of the first semiconductor layer differs from a conductive type of the semiconductor included in the drain region.

According to one embodiment, a semiconductor device includes first, second, third nitride members, first, second, third electrodes, and a first insulating member. The first nitride member includes a first face along a first plane, a second face along the first plane, and a third face. The third face is connected with the first and second faces between the first and second faces. The third face crosses the first plane. The first face overlaps a part of the first nitride member. The second nitride member includes a first nitride region provided at the first face. The third nitride member includes a first nitride portion provided at the second face. The first electrode includes a first connecting portion. The second electrode includes a second connecting portion. The third electrode includes a first electrode portion. The first insulating member includes a first insulating region.

A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, a nitride region, and a first insulating member. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The first semiconductor region includes first to sixth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The sixth partial region is between the fifth and second partial regions. The second semiconductor region includes first and second semiconductor portions. The second semiconductor portion is in contact with the fifth partial region. The nitride region includes a first nitride portion being in contact with the sixth partial region. The first insulating member includes a first insulating region between the third partial region and the first electrode portion.

Current collapse of a normally-on type dual-gate bidirectional switch is suppressed. Dual-gate bidirectional switch includes first gate, first source, second gate, and second source. Control system includes first gate drive circuit, second gate drive circuit, and controller. Controller controls first gate drive circuit and second gate drive circuit. At the time of turning on dual-gate bidirectional switch and when the potential of first source is lower than the potential of second source, controller applies a first positive voltage for a first period between first gate and first source from first gate drive circuit, and applies a voltage smaller than the first positive voltage after the first period has elapsed.