A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.

A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.

The present invention is directed to LED packages and LED displays utilizing water resistant packages with improved structural integrity and customizable attributes. In some embodiments, the improved structural integrity is provided by various features in the lead frame that the casing material encompasses to improve the adhesion between the lead frame and the casing for a stronger, water resistant package. Moreover, in some embodiments the improved structural integrity and water resistance is further provided by cavity features that improve adhesion between the cavity and a protective encapsulant. Some embodiments also provide for packages with a greater overall height than the length of their side-exposed solder pins, which improves gel coverage of the side-exposed solder pins between adjacent packages.

A method can be used for fixing a matrix-free electrophoretically deposited layer on a semiconductor chip. A semiconductor wafer has a carrier substrate and at least one semiconductor chip. The at least one semiconductor chip has an active zone for generating electromagnetic radiation. At least one contact area is formed on a surface of the at least one semiconductor chip facing away from the carrier substrate. A material is electrophoretically deposited on the surface of the at least one semiconductor chip facing away from the carrier substrate in order to form the electrophoretically deposited layer. Deposition of the material on the at least one contact area is prevented. An inorganic matrix material is applied to at least one section of a surface of the semiconductor wafer facing away from the carrier substrate in order to fix the material on the at least one semiconductor chip.

A transparent electrode is made of a first transparent electrode and a second transparent electrode containing a metal atom whose concentration is 10 wt % or less. The first transparent electrode is provided in a region which is overlapped with a p-side pad electrode when seen in a plane view, and the second transparent electrode is provided in a region except for the region which is overlapped with the p-side pad electrode when seen in the plane view. an electric current injected from the p-side pad electrode is diffused into the second transparent electrode, and is injected efficiently into an active layer in a region except for the region which is overlapped with the p-side pad electrode when seen in the plane view. Therefore, the luminous efficiency increases. Also, a contact resistance between the second transparent electrode and the p-type contact layer is low, the element resistance decreases.

A method for manufacturing a power semiconductor device includes: forming a drift region of a first conductivity type, a second emitter region of a second conductivity type, a pn-junction between the second emitter region and drift region, and a first emitter region having a first doping region of the first conductivity type and a second doping region of the first conductivity type; forming a first emitter metallization in contact with the first emitter region to form an ohmic contact between the first emitter metallization and the first doping region, and to form a non-ohmic contact between the first emitter metallization and the second doping region; and forming a second emitter metallization in contact with the second emitter region. The first emitter region is formed using a mask that is aligned with respect to the second emitter region, so that the first and second doping regions are formed in aligned relation.