An array substrate and a display device are provided. A gate insulating layer and a gate electrode are formed on a semiconductor layer in sequence, the gate insulating layer and the gate electrode are located in a middle position of the semiconductor layer and have a uniform shape and size. In a region on the semiconductor layer that is not covered by the gate insulating layer, there is further provided a metal diffusion layer. A barrier layer includes a portion covering the gate insulating layer and the gate electrode and a portion located around the semiconductor layer. A passivation layer covers the semiconductor layer, the gate insulating layer, the gate electrode and the barrier layer. Source and drain electrodes are connected to the metal diffusion layer respectively, and a pixel electrode contacts with the drain electrode.

An array substrate and a display device are provided. A gate insulating layer and a gate electrode are formed on a semiconductor layer in sequence, the gate insulating layer and the gate electrode are located in a middle position of the semiconductor layer and have a uniform shape and size. In a region on the semiconductor layer that is not covered by the gate insulating layer, there is further provided a metal diffusion layer. A barrier layer includes a portion covering the gate insulating layer and the gate electrode and a portion located around the semiconductor layer. A passivation layer covers the semiconductor layer, the gate insulating layer, the gate electrode and the barrier layer. Source and drain electrodes are connected to the metal diffusion layer respectively, and a pixel electrode contacts with the drain electrode.

A semiconductor device having a high on-state current is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a first conductor and a second conductor that are apart from each other over the first oxide; a second insulator covering the first insulator, the first oxide, the first conductor, and the second conductor; a third insulator over the second insulator; a fourth insulator in contact with a first conductor, a side surface of the second conductor, a side surface of the second insulator, and a side surface of the third insulator; a fifth insulator that is over the first oxide and on an inner side of the fourth insulator; a third conductor on an inner side of the fifth insulator; and a sixth insulator that is in contact with a top surface of the fourth insulator and over the third insulator, the fifth insulator, and the third conductor. The fourth insulator is divided to be apart from each other over the first oxide.

A semiconductor device having a high on-state current is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a first conductor and a second conductor that are apart from each other over the first oxide; a second insulator covering the first insulator, the first oxide, the first conductor, and the second conductor; a third insulator over the second insulator; a fourth insulator in contact with a first conductor, a side surface of the second conductor, a side surface of the second insulator, and a side surface of the third insulator; a fifth insulator that is over the first oxide and on an inner side of the fourth insulator; a third conductor on an inner side of the fifth insulator; and a sixth insulator that is in contact with a top surface of the fourth insulator and over the third insulator, the fifth insulator, and the third conductor. The fourth insulator is divided to be apart from each other over the first oxide.

Described are Zn.sub.xCd.sub.1-xS.sub.ySe.sub.1-y/ZnS.sub.zSe.sub.1-z core/shell nanocrystals, CdTe/CdS/ZnS core/shell/shell nanocrystals, optionally doped Zn(S,Se,Te) nano- and quantum wires, and SnS quantum sheets or ribbons, methods for making the same, and their use in biomedical and photonic applications, such as sensors for analytes in cells and preparation of field effect transistors.

Described are Zn.sub.xCd.sub.1-xS.sub.ySe.sub.1-y/ZnS.sub.zSe.sub.1-z core/shell nanocrystals, CdTe/CdS/ZnS core/shell/shell nanocrystals, optionally doped Zn(S,Se,Te) nano- and quantum wires, and SnS quantum sheets or ribbons, methods for making the same, and their use in biomedical and photonic applications, such as sensors for analytes in cells and preparation of field effect transistors.

Provided are an oxide semiconductor excellent in transparency, mobility, and weatherability, etc., and a semiconductor device having the oxide semiconductor, a p-type semiconductor being realizable in the oxide semiconductor. The oxide semiconductor consists of a composite oxide, which has a crystal structure including a pyrochlore structure, containing at least one or more kinds of elements selected from Nb and Ta, and containing Sn element, and its holes become charge carriers by the condition that Sn.sup.4+/(Sn.sup.2++Sn.sup.4+) which is a ratio of Sn.sup.4+ to a total amount of Sn in the composite oxide is 0.124≤Sn.sup.4+/(Sn.sup.2++Sn.sup.4+)≤0.148.

Provided are an oxide semiconductor excellent in transparency, mobility, and weatherability, etc., and a semiconductor device having the oxide semiconductor, a p-type semiconductor being realizable in the oxide semiconductor. The oxide semiconductor consists of a composite oxide, which has a crystal structure including a pyrochlore structure, containing at least one or more kinds of elements selected from Nb and Ta, and containing Sn element, and its holes become charge carriers by the condition that Sn.sup.4+/(Sn.sup.2++Sn.sup.4+) which is a ratio of Sn.sup.4+ to a total amount of Sn in the composite oxide is 0.124≤Sn.sup.4+/(Sn.sup.2++Sn.sup.4+)≤0.148.

The present disclosure relates to a method for manufacturing a semiconductor device structure, comprising the steps of: securing the position of a semiconductor device on a plate; securing the positions of electrodes such that the electrodes face the plate; covering the semiconductor device with an encapsulating material; and separating, from the plate, the semiconductor device covered with the encapsulating material.

To provide an oxide semiconductor with a novel structure. Such an oxide semiconductor is composed of an aggregation of a plurality of InGaZnO.sub.4 crystals each of which is larger than or equal to 1 nm and smaller than or equal to 3 nm, and in the oxide semiconductor, the plurality of InGaZnO.sub.4 crystals have no orientation. Alternatively, such an oxide semiconductor is such that a diffraction pattern like a halo pattern is observed by electron diffraction measurement performed by using an electron beam with a probe diameter larger than or equal to 300 nm, and that a diffraction pattern having a plurality of spots arranged circularly is observed by electron diffraction measurement performed by using an electron beam with a probe diameter larger than or equal to 1 nm and smaller than or equal to 30 nm.