A substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has a plurality of silicon single crystal substrates that are joined and has a thickness of more than 2000 μm, and the plurality of silicon single crystal substrates are produced by a CZ method and have a resistivity of 0.1 Ωcm or lower. This provides: a substrate for an electronic device having a nitride semiconductor film formed on a silicon substrate, where the substrate for an electronic device can suppress a warp and can also be used for a product with a high breakdown voltage; and a method for producing the same.

An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

A method of manufacturing a display device includes: forming a first electrode on a substrate; forming an insulating layer on the substrate and on the first electrode; providing light emitting elements in the insulating layer, each of the light emitting elements having a long axis and a short axis crossing the long axis and being configured to emit light; aligning the light emitting elements such that one end of each of the light emitting elements faces the substrate and the long axis of each of the light emitting elements is arranged in a direction from the substrate toward the insulating layer; patterning the insulating layer to form an insulating pattern exposing another end of each of the light emitting elements; and forming a second electrode electrically connected to the exposed other end of each of the light emitting elements.

A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.

A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.

A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

A semiconductor device includes first and second n-type transistors and first and second p-type transistors. The first n-type transistor includes a first channel layer and a first portion of a high-k dielectric layer over the first channel layer. The second n-type transistor includes a second channel layer and a second portion of the high-k dielectric layer over the second channel layer, wherein the second portion includes a higher amount of an n-type dipole material than the first portion. The first p-type transistor includes a third channel layer and a third portion of the high-k dielectric layer over the third channel layer. The second p-type transistor includes a fourth channel layer and a fourth portion of the high-k dielectric layer over the fourth channel layer, wherein the fourth portion includes a higher amount of a p-type dipole material than the third portion.

A semiconductor device includes first and second n-type transistors and first and second p-type transistors. The first n-type transistor includes a first channel layer and a first portion of a high-k dielectric layer over the first channel layer. The second n-type transistor includes a second channel layer and a second portion of the high-k dielectric layer over the second channel layer, wherein the second portion includes a higher amount of an n-type dipole material than the first portion. The first p-type transistor includes a third channel layer and a third portion of the high-k dielectric layer over the third channel layer. The second p-type transistor includes a fourth channel layer and a fourth portion of the high-k dielectric layer over the fourth channel layer, wherein the fourth portion includes a higher amount of a p-type dipole material than the third portion.

The invention relates to a method, an arrangement and an array, in which a structured contact layer and an elastic carrier layer arranged on a first side of the structured contact layer and connected to the structure contact layer by means of a bonded connection is produced, and in which at least one optoelectronic semiconductor component is arranged on the structured contact layer, on a second side of the structured contact layer, opposing the first side, and is electrically and mechanically connected to the structured contact layer, an elastic conversion layer in an irradiation region being applied to the structured contact layer and the elastic carrier layer in such a way that at least the optoelectronic semiconductor component is embedded in the conversion layer, at least in sections, and a connection region of the structure contact layer remains uncovered.