H01L29/32

Method and device for implanting ions in wafers
11705300 · 2023-07-18 · ·

A method comprising the irradiation of a wafer by an ion beam that passes through an implantation filter. The wafer is heated to a temperature of more than 200° C. The wafer is a semiconductor wafer including SiC, and the ion beam includes aluminum ions.

INSULATED GATE BIPOLAR TRANSISTOR AND PREPARATION METHOD THEREOF, AND ELECTRONIC DEVICE
20230015515 · 2023-01-19 ·

An insulated gate bipolar transistor and a preparation method thereof, and an electronic device. The insulated gate bipolar transistor includes: a drift region; an electrode structure on one side of the drift region; and an electric field stop layer arranged on one side of the drift region away from the electrode structure. The electric field stop layer includes a first sublayer and a second sublayer laminated together. The first sublayer is arranged close to the drift region. A junction depth of the first sublayer is greater than a junction depth of the second sublayer. A peak value of a doping concentration of the first sublayer is less than a peak value of a doping concentration of the second sublayer. A slope of a doping concentration curve of the first sublayer is less than a slope of a doping concentration curve of the second sublayer.

SEMICONDUCTOR DEVICE
20230019632 · 2023-01-19 ·

Provided is a semiconductor device including: an active portion provided thereon; a plurality of trench portions each including a gate conductive portion and arranged in a array direction while extending in a extending direction in the active portion, a conductive portion shape ratio of a trench length to a width of the gate conductive portion array direction being 1,000 or more; a first control pad protruding toward an inner side of the semiconductor substrate from a first outer peripheral side of the semiconductor substrate in a top view; and a first well region provided below the first control pad and to cover the first control pad in the top view, in which a shortest distance between the first well region and a trench center position as a center of a length of the plurality of trench portions in the extending direction in the top view is 1,000 μm or more.

SILICON CARBIDE SEMICONDUCTOR DEVICE
20230223443 · 2023-07-13 · ·

A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

SILICON CARBIDE SEMICONDUCTOR DEVICE
20230223443 · 2023-07-13 · ·

A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

SiC SEMICONDUCTOR DEVICE

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.

MULTI-FINGER HIGH-ELECTRON MOBILITY TRANSISTOR
20230223468 · 2023-07-13 · ·

A multi-finger high-electron mobility transistor and a method of manufacturing such a transistor, and an electronic device including such a transistor is provided. According to an aspect of the present disclosure, an etching step for reducing donor layer thickness and/or performing an ion implantation is used for locally reducing the 2DEG concentration.

Semiconductor device and manufacturing method of 1HE same
11552165 · 2023-01-10 · ·

A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.

SUPPRESSION OF PARASITIC ACOUSTIC WAVES IN INTEGRATED CIRCUIT DEVICES
20230216471 · 2023-07-06 ·

Structures for suppressing parasitic acoustic waves in semiconductor structures and integrated circuit devices are described. Such integrated circuit devices can, typically, produce undesirable acoustic wave resonances, and the acoustic waves can degrade the performance of the devices. In that context, some embodiments described herein relate to spoiling a conductive path that participates in the generation of acoustic waves. Some embodiments relate to spoiling acoustic characteristics of an acoustic resonant structure that may be present in the vicinity of the device. Combined embodiments that spoil the conductive path and acoustic characteristics are also possible.

Power diode and method of manufacturing a power diode

A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body; and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.