A semiconductor device includes a semiconductor substrate including an active region and an outer peripheral region. The active region includes a transistor portion and a diode portion. The outer peripheral region includes a current sensing unit. A lifetime control region including a lifetime killer is provided from the diode portion to at least a part of the transistor portion. The current sensing unit includes a sense transistor non-irradiation region not provided with the lifetime control region and a sense transistor irradiation region provided with the lifetime control region.

Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.

Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.

A method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a SiC single crystal substrate, the method including identifying a total number of large-pit defects caused by micropipes in the SiC single crystal substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, using microscopic and photoluminescence images. Also disclosed is a method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a single crystal substrate, the method including identifying locations of the large-pit defects caused by micropipes in the SiC single crystal substrate and the large-pit defects caused by substrate carbon inclusions in the SiC epitaxial layer, using microscopic and photoluminescence images.

A silicon carbide epitaxial substrate according to a present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer disposed on the silicon carbide substrate. The silicon carbide epitaxial layer includes a boundary surface in contact with the silicon carbide substrate and a main surface opposite to the boundary surface. The main surface has an outer circumferential edge, an outer circumferential region extending within 5 mm from the outer circumferential edge, and a central region surrounded by the outer circumferential region. When an area density of double Shockley stacking faults in the outer circumferential region is defined as a first area density, and an area density of double Shockley stacking faults in the central region is defined as a second area density, the first area density is five or more times as large as the second area density, the second area density is 0.2 cm.sup.−2 or more.

A silicon carbide semiconductor device including a silicon carbide semiconductor substrate. The silicon carbide semiconductor substrate has an active region through which a main current flows, and a termination region surrounding a periphery of the active region in a top view of the silicon carbide semiconductor device. In the top view, the active region is of a rectangular shape, which has two first sides in a <11-20> direction and two second sides in a <1-100> direction. The two first sides are each of a first length, and the two second sides are each of a second length, the first length being longer than the second length.

A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.

A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.

A channel stop and well dopant migration control implant (e.g., of argon) can be used in the fabrication of a transistor (e.g., PMOS), either around the time of threshold voltage adjust and well implants prior to gate formation, or as a through-gate implant around the time of source/drain extension implants. With its implant depth targeted about at or less than the peak of the concentration of the dopant used for well and channel stop implants (e.g., phosphorus) and away from the substrate surface, the migration control implant suppresses the diffusion of the well and channel stop dopant to the surface region, a more retrograde concentration profile is achieved, and inter-transistor threshold voltage mismatch is improved without other side effects. A compensating through-gate threshold voltage adjust implant (e.g., of arsenic) or a threshold voltage adjust implant of increased dose can increase the magnitude of the threshold voltage to a desired level.