Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes an array of termination cells formed in the termination area, the array of termination cells including a first termination cell at an interface to the active area to a last termination cell, each termination cell in the array of termination cells being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the last termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

A method includes forming fin semiconductor features on a substrate. A dopant-containing dielectric material layer is formed on sidewalls of the fin semiconductor features and the substrate. A precise material modification (PMM) process is performed to the dopant-containing dielectric material layer. The PMM process includes forming a first dielectric material layer over the dopant-containing dielectric material layer; performing a tilted ion implantation to the first dielectric material layer so that a top portion of the first dielectric material layer is doped to have a modified etch characteristic different from an etch characteristic of a bottom portion of the first dielectric material layer; and performing an etch process to selectively remove the top portion of the first dielectric material layer and the top portion of the dopant-containing dielectric material layer.

An epitaxial silicon wafer includes a silicon wafer consisting of a COP region in which a nitrogen concentration is 110.sup.8310.sup.9 atoms/cm.sup.3, and an epitaxial silicon film formed on the silicon wafer. When heat treatment for evaluation is applied, a density of BMD formed inside the silicon wafer is 110.sup.8310.sup.9 atoms/cm.sup.3 over the entire radial direction of the silicon wafer. An average density of the BMD formed in an outer peripheral region of the silicon wafer which is a 1-10 mm range separated inward from an outermost periphery thereof is lower than the average density of the BMD formed in a center region. A variation in the BMD density in the outer peripheral region is 3 or less, and a residual oxygen concentration in the outer peripheral region is 810.sup.17 atoms/cm.sup.3 or more.

An epitaxial silicon wafer includes a silicon wafer consisting of a COP region in which a nitrogen concentration is 110.sup.12110.sup.13 atoms/cm.sup.3, and an epitaxial silicon film formed on the silicon wafer. When heat treatment for evaluation is applied, a density of BMD formed inside the silicon wafer is 110.sup.8310.sup.9 atoms/cm.sup.3 over the entire radial direction of the silicon wafer. An average density of the BMD formed in an outer peripheral region of the silicon wafer which is a 1-10 mm range separated inward from an outermost periphery thereof is lower than the average density of the BMD formed in a center region. A variation in the BMD density in the outer peripheral region is 3 or less, and a residual oxygen concentration in the outer peripheral region is 810.sup.17 atoms/cm.sup.3 or more.

This hetero-junction bipolar transistor includes a first n-type GaN layer, an Al.sub.xGa.sub.1-xN layer (0.1x0.5), an undoped GaN layer having a thickness of not less than 20 nm, a Mg-doped p-type GaN layer having a thickness of not less than 100 nm, and a second n-type GaN layer which are sequentially stacked. The first n-type GaN layer and the Al.sub.xGa.sub.1-xN layer form an emitter, the undoped GaN layer and the p-type GaN layer form a base, and the second n-type GaN layer forms a collector. During non-operation, two-dimensional hole gas is formed in a part of the undoped GaN layer near the hetero interface between the Al.sub.xGa.sub.1-xN layer and the undoped GaN layer. When the thickness of the p-type GaN layer is b [nm], the hole concentration of the p-type GaN layer is p [cm.sup.3], and the concentration of the two-dimensional hole gas is P.sub.s [cm.sup.2], pb10.sup.7+P.sub.s110.sup.13 [cm.sup.2] is satisfied.

Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

A novel doping technology for semiconductor wafers has been developed, referred to as a quantum doping process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a quantized set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.

This hetero-junction bipolar transistor includes a first n-type GaN layer, an Al.sub.xGa.sub.1-xN layer (0.1x0.5), an undoped GaN layer having a thickness of not less than 20 nm, a Mg-doped p-type GaN layer having a thickness of not less than 100 nm, and a second n-type GaN layer which are sequentially stacked. The first n-type GaN layer and the Al.sub.xGa.sub.1-xN layer form an emitter, the undoped GaN layer and the p-type GaN layer form a base, and the second n-type GaN layer forms a collector. During non-operation, two-dimensional hole gas is formed in a part of the undoped GaN layer near the hetero interface between the Al.sub.xGa.sub.1-xN layer and the undoped GaN layer. When the thickness of the p-type GaN layer is b [nm], the hole concentration of the p-type GaN layer is p [cm.sup.3], and the concentration of the two-dimensional hole gas is P.sub.s [cm.sup.2], pb10.sup.7+P.sub.s110.sup.13 [cm.sup.2] is satisfied.

In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.