There is provided a nitride semiconductor substrate, including: a substrate configured as an n-type semiconductor substrate; and a drift layer provided on the substrate and configured as a gallium nitride layer containing donors and carbons, wherein a concentration of the donors in the drift layer is 5.010.sup.16/cm.sup.3 or less, and is equal to or more than a concentration of the carbons that function as acceptors in the drift layer, over an entire area of the drift layer, and a difference obtained by subtracting the concentration of the carbons that function as acceptors in the drift layer from the concentration of the donors in the drift layer, is gradually decreased from a substrate side toward a surface side of the drift layer.

An enhancement-mode device includes: a substrate; a channel layer and a barrier layer successively formed on the substrate; an n-type semiconductor layer formed on the barrier layer, a gate region being defined on a surface of the n-type semiconductor layer; a groove that is formed in the gate region and at least partially runs through the n-type semiconductor layer; and a p-type conductor material that is formed on the surface of the n-type semiconductor layer and at least fills the inside of the groove.

A high-quality nitride crystal can be produced efficiently by charging a nitride crystal starting material that contains tertiary particles having a maximum diameter of from 1 to 120 mm and formed through aggregation of secondary particles having a maximum diameter of from 100 to 1000 m, in the starting material charging region of a reactor, followed by crystal growth in the presence of a solvent in a supercritical state and/or a subcritical state in the reactor, wherein the nitride crystal starting material is charged in the starting material charging region in a bulk density of from 0.7 to 4.5 g/cm.sup.3 for the intended crystal growth.

A silicon carbide semiconductor substrate includes an epitaxial layer. A difference of a donor concentration and an acceptor concentration of the epitaxial layer is within a range from 110.sup.14/cm.sup.3 to 110.sup.15/cm.sup.3. Further, the donor concentration and the acceptor concentration of the epitaxial layer are a concentration unaffected by an impurity inside epitaxial growth equipment.

A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer. The HEMT also includes a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer. The HEMT further includes n-doped protuberance(s) disposed above the AlGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.

A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.

Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

This disclosure relates to methods of forming bipolar transistors, such as heterojunction bipolar transistors. The methods may include forming a sub-collector over a substrate, forming a first portion of a collector over the sub-collector and doping a second portion of the collector to form a doping spike. The method may further include forming a third portion of the collector over the doping spike and forming a base of the bipolar transistor over the third portion of the collector.