A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the drift region. The structure further includes an n-type source region contained in the p-type body region; an n-type drain region contained in the n-type drift region; a gate electrode disposed on a gate dielectric overlying a portion of the p-type body region and the n-type drift region and an electrically conductive field shield member disposed within the n-type drift region at least partially beneath the p-type body region and generally parallel to the gate electrode. The electrically conductive buried field shield member is contained within and surrounded by a layer of buried field shield oxide and is common to both a first LD MOSFET and a second LD MOSFET that are connected in parallel. Methods to fabricate the structure are also disclosed.

Provided is a semiconductor device comprising: a semiconductor substrate; a gate trench section that is provided from an upper surface to an inside of the semiconductor substrate and extends in a predetermined extending direction on the upper surface of the semiconductor substrate; a mesa section in contact to the gate trench section in an arrangement direction orthogonal the extending direction; and an interlayer dielectric film provided above the semiconductor substrate; wherein the interlayer dielectric film is provided above at least a part of the gate trench section in the arrangement direction; a contact hole through which the mesa section is exposed is provided to the interlayer dielectric film; and a width of the contact hole in the arrangement direction is equal to or greater than a width of the mesa section in the arrangement direction.

A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors.

A semiconductor device includes a high-voltage semiconductor transistor chip having a front side and a backside. A low-voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. The semiconductor device further includes a dielectric inorganic substrate having a first side and a second side opposite the first side. A pattern of first metal structures runs through the dielectric inorganic substrate and is connected to the low-voltage load electrode. At least one second metal structure runs through the dielectric inorganic substrate and is connected to the control electrode. The front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate. The dielectric inorganic substrate has a thickness measured between the first side and the second side of at least 50 μm.

A terminal structure of a power device includes a substrate and a plurality of field limiting rings disposed on a first surface of the substrate. The substrate includes a drift layer and a doped layer. The doped layer is formed through diffusion inward from the first surface of the substrate. The doped layer and the drift layer are a first conductivity type, and an impurity concentration of the doped layer is greater than an impurity concentration of the drift layer. The field limiting rings are a second conductivity type. In the terminal structure, lateral diffusion of impurities in the field limiting rings is limited through a design of the doped layer.

A semiconductor device includes: a semiconductor substrate, a gate oxide layer, and a polysilicon field plate. The semiconductor substrate includes a drift region and a well region. An end of the drift region is arranged with a drain region, and an end of the well region is arranged with a source region. The gate oxide layer is arranged on the semiconductor substrate and disposed between the source region and the drain region. The polysilicon field plate is arranged on the gate oxide layer. At least a portion of the polysilicon field plate is projected onto the drift region and includes at least two field-plate regions. While the semiconductor device is operating, in a direction from an end of the drift region near the well region approaching the drain region, an equivalent electrical thickness of an insulating layer between the polysilicon field plate and the drift region gradually increases.

A semiconductor device includes a semiconductor substrate, a body layer, a source region, a drift layer, a drain region, a gate insulating film, and a gate electrode. The semiconductor substrate has an active layer. An element region is included in the active layer and partitioned by a trench isolation portion. The body layer is disposed at a surface layer portion of the active layer. The source region is disposed at a surface layer portion of the body layer. The drift layer is disposed at the surface layer portion of the active layer. The drain region is disposed at a surface layer portion of the drift layer. The gate insulating film is disposed on a surface of the body layer. The gate electrode is disposed on the gate insulating film. One of the source region and the drain region being a high potential region is surrounded by the other one being a low potential region.

A semiconductor device includes a semiconductor part, a first electrode at a back surface of the semiconductor part; a second electrode at a front surface of the semiconductor part; third and fourth electrodes provided between the semiconductor part and the second electrode. The third and fourth electrodes are arranged in a first direction along the front surface of the semiconductor part. The third electrode is electrically insulated from the semiconductor part by a first insulating film. The third electrode is electrically insulated from the second electrode by a second insulating film. The fourth electrode is electrically insulated from the semiconductor part by a third insulating film. The fourth electrode is electrically isolated from the third electrode. the third and fourth electrodes extend into the semiconductor part. The fourth electrode includes a material having a larger thermal conductivity than a thermal conductivity of a material of the third electrode.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.