A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.

A semiconductor structure includes a substrate having an active region and an isolation region, an insulating layer disposed on the substrate, a seed layer disposed on the insulating layer, a compound semiconductor layer disposed on the seed layer, a gate structure in the active region disposed on the compound semiconductor layer, an isolation structure in the isolation region disposed on the substrate, a pair of through-substrate vias in the isolation region disposed on the opposite sides of the gate structure, and a source structure and a drain structure disposed on the substrate and on the opposite sides of the gate structure. The pair of through-substrate vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure electrically connect the seed layer by the pair of through-substrate vias.

The present disclosure relates to a semiconductor device and an electronic apparatus that make it possible to provide a higher voltage resistance. An outer-peripheral structure region is provided in an n-type well on a surface of a semiconductor substrate, the outer-peripheral structure region being arranged to surround an outer periphery of a region in which a plurality of semiconductor elements is formed. Further, an anode is arranged in an innermost in the outer-peripheral structure region, and a plurality of guard rings is multiply arranged on an outside of the anode. Furthermore, a field plate covering the anode and a field plate covering a guard ring adjacent to the anode are formed to be electrically connected to each other so as to be combined. The present technology is applicable to, for example, various semiconductor devices.

A semiconductor structure includes a substrate having an active region and an isolation region, an insulating layer disposed on the substrate, a seed layer disposed on the insulating layer, a compound semiconductor layer disposed on the seed layer, a gate structure in the active region disposed on the compound semiconductor layer, an isolation structure in the isolation region disposed on the substrate, a pair of through-substrate vias in the isolation region disposed on the opposite sides of the gate structure, and a source structure and a drain structure disposed on the substrate and on the opposite sides of the gate structure. The pair of through-substrate vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure electrically connect the seed layer by the pair of through-substrate vias.

A semiconductor device includes a semiconductor body, a first electrode on a back surface of the semiconductor body, second and third electrodes provided on a front surface of the semiconductor body, a first film linking the second electrode and the third electrode, and a second film between the semiconductor body and the first film. The first film has a higher resistivity than the first semiconductor body, and the second film is insulative. The second film includes a first-film-thickness portion and a second-film-thickness portion. The first-film-thickness portion has a first film thickness along a first direction directed from the first electrode toward the second electrode. The second-film-thickness portion has a second film thickness along the first direction thicker than the first film thickness. The first-film-thickness portion and the second-film-thickness portion surround the second electrode. The first film extends along surfaces of the first-film-thickness portion and the second-film-thickness portion.

Some embodiments relate to a method. In the method, a semiconductor substrate is provided. Dopant impurities of a first dopant conductivity are implanted into the semiconductor substrate to form a body region. A gate dielectric and a field oxide region are formed over the semiconductor substrate. A polysilicon layer is formed over the gate dielectric and field oxide region. The polysilicon layer is patterned to concurrently form a conductive gate electrode over the gate dielectric and a resistor structure over the field oxide region. The resistor structure is perimeterally bounded by an inner edge of the conductive gate electrode. Dopant impurities of a second dopant conductivity, which is opposite the first dopant conductivity, are implanted into the semiconductor substrate to form a source region and a drain region. The drain region is perimeterally bounded by the inner edge of the conductive gate electrode.

The semiconductor device includes: a fourth impurity layer disposed in a state of being connected to the outermost peripheral second impurity layer and being separated from the first impurity layer between the outermost peripheral second impurity layer and the first impurity layer of the terminal portion, the fourth impurity layer having a second conductivity type and having an impurity concentration lower than an impurity concentration of the second impurity layer; an insulating film disposed on at least a part of the terminal portion, the insulating film having a first opening on the first impurity layer; and an electrode disposed on the insulating film, the electrode connected to the first impurity layer via the first opening.

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a substrate, a first doped region disposed in the substrate and doped with a first doping polarity, and a second doped region disposed in the substrate and horizontally outside the first doped region. The second doped region is doped with a second doping polarity opposite to the first doping polarity. The semiconductor device further includes a third doped region disposed completely within the first doped region. The third doped region is doped with the second doping polarity. The semiconductor device further includes a first isolation structure disposed over the first doped region and spaced apart from the second doped region and the third doped region, a second isolation structure disposed over the first doped region and the third doped region, and a resistor disposed over the first isolation structure.

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.