Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

A semiconductor device includes a capacitance adjusting region. The capacitance adjusting region includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a plurality of control trench gates. The first semiconductor layer is provided as a surface layer at an upper surface of the semiconductor substrate. The second semiconductor layer is selectively provided at an upper surface of the first semiconductor layer. The second semiconductor layer contacts a side surface of each of the control trench gates. The first semiconductor layer and the second semiconductor layer are electrically connected to an emitter electrode of a transistor. A control trench electrode of at least one control trench gate is electrically connected to a gate electrode of the transistor.

A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers. Trenches penetrate through the second semiconductor region and reach the first semiconductor region. Each of the trenches may include a gate electrode, and an insulating film insulating the gate electrode from the first semiconductor region and the second semiconductor region. An upper electrode is electrically connected to the second semiconductor region and the third semiconductor region. A fourth semiconductor region of the second conductivity type is arranged on an outer side of the trench of which the gate electrode is an outermost gate electrode in a plan view. An edge trench is arranged on an outer side of the fourth semiconductor region. The fourth semiconductor region is electrically connected to the upper electrode and a bottom of the fourth semiconductor may be arranged deeper than a bottom of the second semiconductor region.

The present application relates to a semiconductor transistor device that includes a Schottky diode electrically connected in parallel to a body diode formed between a body region and a drift region. A diode junction of the Schottky diode is formed adjacent to the drift region and is arranged vertically above a lower end of the body region.

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs, and a Schottky diode area including a plurality of Schottky diodes formed in the drift region having the superjunction structure. Each of the integrated Schottky diodes includes a Schottky contact between a lightly doped semiconductor layer and a metallic layer.

A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region overlying a shield region in an epitaxial or crystalline layer of the device. The polysilicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

A power device includes: a diode section; a semiconductor body; a drift region extending into the diode section; trenches in the diode section and extending along a vertical direction into the semiconductor body, two adjacent trenches defining a respective mesa portion in the semiconductor body; a body region in the mesa portions; in the diode section, a barrier region between the body and drift regions and having a dopant concentration at least 100 times greater than an average dopant concentration of the drift region and a dopant dose greater than that of the body region. The barrier region has a lateral structure according to which at least 50% of the body region in the diode section is coupled to the drift region at least by the barrier region, and at least 5% of the body region in the diode section is coupled to the drift region without the barrier region.

A semiconductor device is described. The semiconductor device includes: a semiconductor substrate; an electrode structure on or in the semiconductor substrate, the electrode structure including an electrode and an insulating material that separates the electrode from the semiconductor substrate; and a strain-inducing material embedded in the electrode. The electrode structure adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. The electrode is under either tensile or compressive stress in the first direction. The strain-inducing material either enhances or at least partly counteracts the stress of the electrode in the first direction. Methods of producing the semiconductor device are also described.

A semiconductor device is described. The semiconductor device includes: a Si substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the Si substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.