A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape.

A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

A transistor, integrated semiconductor device and methods of making are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.

It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

A memory cell includes a transistor and a capacitor. The transistor includes a gate electrode, a gate dielectric disposed over the gate electrode, a channel feature disposed over the gate dielectric and overlapping the gate electrode, a source electrode disposed over the channel feature and electrically connected to the capacitor, and two drain electrodes disposed over the channel feature. The drain electrodes are disposed at opposite sides of the source electrode. The channel feature has a first channel portion extending between and interconnecting one drain electrode and the source electrode, and a second channel portion extending between and interconnecting the other drain electrode and the source electrode. The gate electrode overlaps both of the first channel portion and the second channel portion of the channel feature.

The present disclosure relates to methods of manufacturing Ohmic contacts on a silicon carbide (SiC) substrate including providing a 4H—SiC or 6H—SiC substrate, implanting dopants into a surface region of the 4H—SiC or 6H—SiC substrate, annealing the implanted surface regions to form a 3C—SiC layer, and depositing a metal layer on the 3C—SiC layer. An implanting sequence of the implantation of dopants includes a plurality of plasma deposition acts with implantation energy levels including at least two different implantation energy levels. The implantation energy levels and one or more implantation doses of the plurality of plasma deposition acts are selected to form a 3C—SiC layer in the surface region of the 4H—SiC or 6H—SiC substrate during the annealing act. A method of manufacturing a semiconductor device having a structure including at least three layers including a 4H—SiC or 6H—SiC layer, a 3C—SiC layer, and a metal layer, by applying one or more of the techniques described herein, and semiconductor devices obtained with one or more of the techniques described herein are described.

A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.

Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.