To provide a semiconductor device in which a large current can flow. To provide a semiconductor device which can be driven stably at a high driving voltage. The semiconductor device includes a semiconductor layer, a first electrode and a second electrode electrically connected to the semiconductor layer and apart from each other in a region overlapping with the semiconductor layer, a first gate electrode and a second gate electrode with the semiconductor layer therebetween, a first gate insulating layer between the semiconductor layer and the first gate electrode, and a second gate insulating layer between the semiconductor layer and the second gate electrode. The first gate electrode overlaps with part of the first electrode, the semiconductor layer, and part of the second electrode. The second gate electrode overlaps with the semiconductor layer and part of the first electrode, and does not overlap with the second electrode.

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

A trench-type MESFET includes an n-type semiconductor layer including a Ga.sub.2O.sub.3-based single crystal and including plural trenches opening on one surface, first insulators respectively buried in bottom portions of the plural trenches, gate electrodes respectively buried in the plural trenches so as to be placed on the first insulators and so that side surfaces thereof are in contact with the n-type semiconductor layer, a source electrode connected to a mesa-shaped portion between the adjacent trenches of the n-type semiconductor layer, second insulators respectively buried in the plural trenches so as to be placed on the gate electrodes to insulate the gate electrodes and the source electrode, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on a side opposite to the source electrode.

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

A nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, a third nitride semiconductor layer that is disposed on the second nitride semiconductor layer, has a ridge portion at least at a portion thereof, and contains an acceptor type impurity, a gate electrode that is disposed on the ridge portion, and a source electrode and a drain electrode that, on the second nitride semiconductor layer, are disposed across the ridge portion from each other, and has an active region and a nonactive region. The nonactive region has a first region and a film thickness of the second nitride semiconductor layer in the first region differs from a film thickness of the second nitride semiconductor layer in a region of the active region in which the ridge portion, the source electrode, and the drain electrode are not formed.

A vertical-structure field-effect transistor comprises: a gate electrode, which is formed on a substrate and has a horizontal plane extending in the planar direction and a vertical plane extending in the height direction; a gate insulating layer for covering the gate electrode; a vertical channel which is formed on the gate insulating layer and has a channel formed in the height direction; a source electrode formed to make contact with one end of the vertical channel; and a drain electrode formed to make contact with the other end of the vertical channel and formed at a height level different from that of the source electrode, wherein channel on/off of the vertical channel is controlled by means of an electric field formed from the vertical plane of the gate electrode to the vertical channel, and the source electrode and/or the drain electrode can be non-overlapping on the gate electrode in the height direction of the gate electrode.

An electronic device for storing, controlling and manipulating electron or hole spin based semiconductor qubits, the device including an electrically insulating layer and on a front face of the insulating layer, a trapping structure for electrons or holes which includes: a channel portion including at least one layer portion of semiconductor material, as well as a plurality of gates distributed for trapping at least one electron or hole in the channel portion, and on the back side of the insulating layer, an electrical track extending parallel to the insulating layer, for generating an oscillating magnetic field acting on the at least one electron or hole trapped in the trapping structure.

An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and on the first gate structure. In addition, at least a portion of the second gate structure is on a central portion of the isolation structure and between first and second end portions of the isolation structure.

A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.

A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.