VERTICAL-STRUCTURE FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

Abstract

A vertical-structure field-effect transistor comprises: a gate electrode, which is formed on a substrate and has a horizontal plane extending in the planar direction and a vertical plane extending in the height direction; a gate insulating layer for covering the gate electrode; a vertical channel which is formed on the gate insulating layer and has a channel formed in the height direction; a source electrode formed to make contact with one end of the vertical channel; and a drain electrode formed to make contact with the other end of the vertical channel and formed at a height level different from that of the source electrode, wherein channel on/off of the vertical channel is controlled by means of an electric field formed from the vertical plane of the gate electrode to the vertical channel, and the source electrode and/or the drain electrode can be non-overlapping on the gate electrode in the height direction of the gate electrode.

Claims

1. A vertical-structure field-effect transistor comprising: a gate electrode formed on a substrate and having a horizontal plane extending in a plane direction and a vertical plane extending in a height direction; a gate insulating layer covering the gate electrode; a vertical channel formed on the gate insulating layer, in which a channel is formed in the height direction; a source electrode coming into contact with one end of the vertical channel; and a drain electrode coming into contact with an opposite end of the vertical channel, and formed at a height level different from a height level of the source electrode, wherein a channel on-off state of the vertical channel is controlled by an electric field formed to the vertical channel in the vertical plane of the gate electrode, and at least one of the source electrode and the drain electrode does not overlap (non-overlaps) the gate electrode in the height direction of the gate electrode.

2. The vertical-structure field-effect transistor of claim 1, wherein the source electrode, the vertical channel, and the drain electrode include semiconductor components identical to each other, and the source electrode and the drain electrode further include ions for increasing electrical conductivity.

3. The vertical-structure field-effect transistor of claim 2, wherein the gate electrode is further formed thereon with a hard film having an etching rate lower than an etching rate of the gate electrode.

4. The vertical-structure field-effect transistor of claim 1, wherein the source electrode is formed below one end of the vertical channel, and the drain electrode is formed below an opposite end of the vertical channel.

5. The vertical-structure field-effect transistor of claim 1, wherein the source electrode is formed above one end of the vertical channel, and the drain electrode is formed above an opposite end of the vertical channel.

6. A method for manufacturing a vertical-structure field-effect transistor, the method comprising: preparing a substrate; forming a preliminary gate electrode layer on the substrate; forming a hard film having an etching rate lower than an etching rate of the gate electrode on the preliminary gate electrode layer; patterning the hard film; using the hard film as a mask and patterning the gate electrode to have a horizontal plane extending in a plane direction and a vertical plane extending in a height direction; forming a gate insulating layer; forming a semiconductor layer on the gate insulating layer, and patterning the formed semiconductor layer to have a horizontal portion extending in the plane direction and a vertical portion extending in the height direction; and forming one end of the horizontal portion as a source electrode and forming an opposite end of the horizontal portion as a drain electrode, by implanting ions having high electrical conductivity in the height direction.

7. The method of claim 6, wherein at least one of the source electrode and the drain electrode non-overlaps the gate electrode in the height direction.

8. A method for manufacturing a vertical-structure field-effect transistor, the method comprising: preparing a substrate; forming a preliminary gate electrode layer on the substrate; forming a hard film having an etching rate lower than an etching rate of the gate electrode on the preliminary gate electrode layer; patterning the hard film; using the hard film as a mask and patterning the preliminary gate electrode layer to have a horizontal plane extending in a plane direction and a vertical plane extending in a height direction; forming a gate insulating layer; forming a preliminary electrode layer on the gate insulating layer, and first patterning the formed preliminary electrode layer to have a horizontal portion extending in the plane direction and a vertical portion extending in the height direction; performing a second patterning of selectively removing only the vertical portion of the horizontal portion and the vertical portion from the first patterned preliminary electrode layer, thereby forming source and drain electrodes; and forming a semiconductor layer on the source and drain electrodes, and patterning the formed semiconductor layer, thereby forming a vertical channel for connecting the source electrode and the drain electrode in the height direction.

9. The method of claim 8, wherein at least one of the source electrode and the drain electrode non-overlaps the gate electrode in the height direction.

10. The method of claim 8, wherein the vertical portion of the first patterning has a thickness thinner than a thickness of the horizontal portion.

11. A method for manufacturing a vertical-structure field-effect transistor, the method comprising: preparing a substrate; forming a preliminary gate electrode layer on the substrate; forming a hard film having an etching rate lower than an etching rate of the gate electrode on the preliminary gate electrode layer; patterning the hard film; using the hard film as a mask and patterning the preliminary gate electrode layer as a gate electrode having a horizontal plane extending in a plane direction and a vertical plane extending in a height direction; forming a gate insulating layer; forming a semiconductor layer on the gate insulating layer, and continuously forming a preliminary electrode layer on the semiconductor layer; forming a vertical channel extending in the height direction by patterning the semiconductor layer with the same mask, and forming the preliminary electrode layer as an intermediate electrode layer having a vertical portion extending in the height direction and a horizontal portion extending in the plane direction; and forming source and drain electrodes by removing the vertical portion of the intermediate electrode layer.

12. The method of claim 11, wherein at least one of the source electrode and the drain electrode non-overlaps the gate electrode in the height direction.

13. The method of claim 11, wherein the vertical portion of the forming of the intermediate electrode layer has a thickness thinner than a thickness of the horizontal portion.

Description

DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a view for explaining a vertical-structure field-effect transistor according to one embodiment of the present invention.

[0029] FIGS. 2 and 3 are flowcharts for explaining the manufacturing method of the vertical-structure field-effect transistor according to the first embodiment of the present invention.

[0030] FIGS. 4 to 20 are views for explaining in detail each step of method for manufacturing the vertical-structure field-effect transistor according to the first embodiment of the present invention.

[0031] FIGS. 21 and 22 are flowcharts for explaining the method for manufacturing the vertical-structure field-effect transistor according to a second embodiment of the present invention.

[0032] FIGS. 23 to 40 are views for explaining in detail each step of method for manufacturing the vertical-structure field-effect transistor according to a second embodiment of the present invention.

[0033] FIGS. 41 and 42 are flowcharts for explaining the method for manufacturing the vertical-structure field-effect transistor according to a third embodiment of the present invention.

[0034] FIGS. 43 to 58 are views for explaining in detail each step of method for manufacturing the vertical-structure field-effect transistor according to a third embodiment of the present invention.

BEST MODE

Mode for Invention

[0035] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical idea of the present invention is not limited to the exemplary embodiments described herein and may be embodied in other forms. Further, the embodiments are provided to enable contents disclosed herein to be thorough and complete and provided to enable those skilled in the art to fully understand the idea of the present invention.

[0036] In the specification herein, when one component is mentioned as being on the other component, it signifies that the one component may be placed directly on the other component or a third component may be interposed therebetween. In addition, in drawings, thicknesses of layers and areas may be exaggerated to effectively describe the technology of the present invention.

[0037] In addition, although terms such as first, second and third are used to describe various components in various embodiments of the present specification, the components will not be limited by the terms. The above terms are used merely to distinguish one component from another. Accordingly, a first component referred to in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein may also include a complementary embodiment. In addition, the term “and/or” is used herein to include at least one of the components listed before and after the term.

[0038] The singular expression herein includes a plural expression unless the context clearly specifies otherwise. In addition, it will be understood that the term such as “include” or “have” herein is intended to designate the presence of feature, number, step, component, or a combination thereof recited in the specification, and does not preclude the possibility of the presence or addition of one or more other features, numbers, steps, components, or combinations thereof. In addition, the term “connection” is used herein to include both indirectly connecting a plurality of components and directly connecting the components.

[0039] In addition, in the following description of the embodiments of the present invention, the detailed description of known functions and configurations incorporated herein will be omitted when it possibly makes the subject matter of the present invention unclear unnecessarily.

[0040] FIG. 1 is a view for explaining a vertical-structure field-effect transistor according to one embodiment of the present invention.

[0041] Referring to FIG. 1, a vertical-structure field-effect transistor 100 according to one embodiment of the present invention may include at least one of a substrate 100, a lower insulating film 101, a gate electrode 102, a gate insulating layer 103, a vertical channel 104, source/drain electrodes 105 and 106, and an upper insulating film 107. Hereinafter, each configuration will be described in detail.

[0042] The substrate 100 may be formed of at least one of glass and plastic-based materials. For example, in the case of plastic-based material, the substrate 100 may include at least one of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polycarbonate (PC). When the substrate 100 is formed of the plastic-based material, it may have flexible properties. However, the substrate 100 may have flexible properties even when being formed of a glass-based material.

[0043] A lower insulating film 101 may be provided on the substrate 100. The lower insulating film 101 may include at least one of organic and inorganic materials. When the lower insulating film 101 is the inorganic material, the lower insulating film may be formed of a silicon nitride film (SiNx) or a silicon oxide film (SiOx), and the material of the lower insulating film 101 is not limited thereto. In addition, the lower insulating film 101 may be omitted.

[0044] The gate electrode 102 may be provided on the lower insulating film 101. The gate electrode 102 may be formed of at least one metal among copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum (Ta) and tungsten (W), and may have a structure in which a single layer or a plurality of metals are laminated.

[0045] The gate insulating layer 103 may be provided on the gate electrode 102. The gate insulating layer 103 forms an electric field between the vertical channel 104 and the gate electrode 102 to be described later, but may function as an insulating film that blocks the flow of current.

[0046] The vertical channel 104 may be formed of at least one of materials, for example, amorphous silicon, single crystal silicon, and oxide semiconductor. For example, when the vertical channel 104 is formed of an oxide semiconductor, the vertical channel 104 may be formed of indium-galium-zinc oxide (IGZO). However, the vertical channel 104 is not limited to a specific oxide semiconductor.

[0047] The source and drain electrodes 105 and 106 may be energized via the vertical channel 104 as a current path. The source and drain electrodes 105 and 106 may be formed as a part of the vertical channel 104, and may be formed as a different layer from the vertical channel 104. Specific details of the source and drain electrodes 105 and 106 will be described to in the description of the first to third embodiments below.

[0048] The source and drain electrodes 105 and 106 may be formed as a single layer or multiple layers. In the case of single layer, it may be formed of at least one material or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). When the source and drain electrodes 105 and 106 are formed as multiple layers, the multiple layers may be formed as a double layer of molybdenum/aluminum-neodymium, molybdenum/aluminum, titanium/aluminum, or copper/molytitanium, or as a triple layer of molybdenum/aluminum-neodymium/molybdenum, molybdenum/aluminum/molybdenum, titanium/aluminum/titanium, or molytitanium/copper/molytitanium.

[0049] According to one embodiment, the source electrode 105 and the drain electrode 106 may be provided at different height levels, that is, different heights in the Y-axis direction of FIG. 1.

[0050] The upper insulating film 107 may be provided on the source and drain electrodes 105 and 106, and the upper insulating film 107 has a through-hole, so that a connection electrode 08 electrically connected to the source and drain electrodes 105 and 106 through the through-hole may be provided.

[0051] According to one embodiment of the present invention, the gate electrode 102 may have a horizontal plane extending in a plane direction (X-axis direction of FIG. 1) and a vertical plane extending in a height direction (Y-axis direction of FIG. 1).

[0052] The vertical channel 104 is electrically on/off controlled according to the electric field from the gate electrode 102, in which the direction of the electric field (E in FIG. 1) from the gate electrode 102 may be a plane direction of the gate electrode 102.

[0053] Accordingly, the direction (I in FIG. 1) of movement of the current in the vertical channel 104 may be in a height direction (Y-axis direction in FIG. 1), which is a plane direction of the vertical channel 104.

[0054] Further, according to one embodiment, at least one of the source electrode 105 and the drain electrode 106 may non-overlap the gate electrode 102. Referring to FIG. 1, the source electrode 105 may non-overlap the gate electrode 102 in the Y-axis direction of FIG. 1.

[0055] In other words, the vertical channel 104 allows a current to flow in the height direction of the vertical channel 104 (Y direction in FIG. 1), so that a space for allowing the source electrode 105 to non-overlap the gate electrode 102 may be provided.

[0056] Accordingly, at least one of the source and drain electrodes 105 and 106 non-overlaps the gate electrode 102, so that the parasitic capacitance and the leakage current can be minimized.

[0057] Since the vertical-structure field-effect transistor according to one embodiment of the present invention may be manufactured by various methods, the first to third embodiments will be described below with reference to FIGS. 2 to 58.

[0058] For the reference, when a reference numeral used during describing each manufacturing method is the same as the component in the previously described embodiments, it performs the corresponding function, and accordingly, the detailed description will be omitted.

[0059] FIGS. 2 and 3 are flowcharts for explaining the method for manufacturing the vertical-structure field-effect transistor according to the first embodiment of the present invention. FIGS. 4 to 20 are views for explaining each step in detail of the method for manufacturing the vertical-structure field-effect transistor according to the first embodiment of the present invention.

[0060] Referring to FIGS. 2 and 3, the vertical-structure field-effect transistor according to the first embodiment of the present invention may include at least one step of: preparing a substrate (S100), forming a preliminary gate electrode layer on the substrate (S102), forming a hard film having an etching rate lower than an etching rate of the gate electrode on the gate electrode (S104), patterning the hard film (S106), using the hard film as a mask and patterning the gate electrode to have a horizontal plane extending in a plane direction and a vertical plane extending in a height direction (S108), forming a gate insulating layer (S110), forming a semiconductor layer on the gate insulating layer, and patterning the formed semiconductor layer to have a horizontal portion extending in the plane direction and a vertical portion extending in the height direction (S112), forming one end of the horizontal portion as a source electrode and forming an opposite end of the horizontal portion as a drain electrode by implanting ions having high electrical conductivity in the height direction (S114), and forming a protective layer, forming a contact hole in the protective layer, and then forming a connection electrode in the contact hole (S116).

[0061] Hereinafter, each step will be described in detail.

[0062] S100

[0063] The substrate 200 may be prepared, and a lower insulating film 201 may be formed on the substrate 200 (see FIGS. 4 and 5).

[0064] S102 and S104

[0065] A preliminary gate electrode layer 202 and a hard film 203 may be formed on the lower insulating film 201 (see FIG. 6). When the gate electrode 202 is etched, for example, dry etched vertically (in the Y-axis direction of FIG. 1), the hard film 203 may function as a hard mask. The hard film 203 may include at least one of, for example, silicon nitride, silicon oxide, and aluminum oxide.

[0066] S106

[0067] The hard film 203 may be patterned. To this end, a photo resistor 203-1 may be formed on the hard film 203 (see FIG. 7). Thereafter, only the gate electrode-shaped part may be selectively removed through a photomask, so that the photoresist 203-1 remains (see FIG. 8). Thereafter, the hard film 203 may be patterned to correspond to the shape of the remaining photoresistor 203-1 (see FIG. 9). Thereafter, the remaining photoresistor 203-1 may be removed (see FIG. 10).

[0068] S108

[0069] The preliminary gate electrode layer 202 may be patterned as a gate electrode 202. The remaining hard film 203 may function as a mask. For example, the gate electrode 202 may be formed through an etching plasma 203-2 process (see FIG. 11). Since the hard film 203 on the gate electrode 202 has a very high etch selectivity rate, the vertical plane (the Y-axis direction of FIG. 1) of the gate electrode 202 may have an excellent shape profile.

[0070] S110

[0071] A gate insulating layer 204 may be formed.

[0072] The gate insulating layer 204 may be formed along the shape of the gate electrode 202 having the vertical plane (see FIG. 12).

[0073] S112

[0074] A vertical channel 205 may be formed.

[0075] To this end, a semiconductor layer 205 may be formed on the gate insulating layer 204 (see FIG. 13).

[0076] The semiconductor layer 205 may be patterned and formed as a vertical channel (see FIG. 14). The formed vertical channel 205 may have a vertical portion extending in the height direction and a horizontal portion extending in the plane direction. According to an embodiment of the present invention, the vertical portion may overlap the gate electrode in the plane direction (X-axis direction of FIG. 1).

[0077] S114

[0078] Source and drain electrodes may be formed.

[0079] To this end, an ion implantation 205-1 process may be performed in which ions are accelerated in the vertical direction (Y-axis direction of FIG. 1) with respect to the substrate in the horizontal portion of the vertical channel 205 (see FIG. 15). Accordingly, ions are implanted at a high density in the horizontal portion, thereby increasing the electrical conductivity, so that source and drain electrodes 207 may be formed (see FIG. 16). In this case, the source and drain electrodes 207 may be manufactured based on the semiconductor layer.

[0080] In addition, the ions are implanted in the vertical direction, so that the implantation of ions may be minimized in the vertical portion of the vertical channel 205. This is because the vertical portion of the vertical channel 205 may have the more vertical shape since the vertical plane profile of the gate electrode 20 is excellent. Accordingly, the vertical portion of the vertical channel 205 may maintain an intrinsic semiconductor characteristic.

[0081] S116

[0082] An upper insulating film 208 may be formed (see FIG. 17). Contact holes 206-1 and 207-1 for contact with the source and drain electrodes may be formed at one side of the upper insulating film 208 (see FIG. 18). Connection electrodes 209 may be formed to electrically come into contact with the source and drain electrodes 206 and 207 through the formed contact holes 206-1 and 207-1, respectively.

[0083] Through the above process, the vertical-structure field-effect transistor 200 according to the first embodiment may be manufactured (see FIG. 20).

[0084] Referring to FIG. 20, the vertical channel 205 may be formed accurately in the height direction (Y-axis direction of FIG. 20). Accordingly, the vertical channel 205 may still maintain the intrinsic semiconductor properties despite the ion implantation process for forming the source and drain electrodes 206 and 207. Further, as previously described with reference to FIG. 1, the at least one of the source and drain electrodes 206 and 207 non-overlaps the gate electrode 202 in the height direction (Y-axis direction of FIG. 20), so that the leakage current and the parasitic capacitance can be minimized.

[0085] Hereinafter, a vertical-structure field-effect transistor 300 according to a second embodiment of the present invention will be described with reference to FIGS. 21 to 40.

[0086] FIGS. 21 and 22 are flowcharts for explaining the method for manufacturing the vertical-structure field-effect transistor according to a second embodiment of the present invention. FIGS. 23 to 40 are views for explaining each step in detail of the method for manufacturing the vertical-structure field-effect transistor according to a second embodiment of the present invention.

[0087] Referring to FIGS. 21 and 22, the vertical-structure field-effect transistor according to a second embodiment of the present invention may include at least one step of: preparing a substrate (S200), forming a preliminary gate electrode layer on the substrate (S202), forming a hard film having an etching rate lower than an etching rate of the gate electrode on the preliminary gate electrode layer (S204), patterning the hard film (S206), using the hard film as a mask and patterning the preliminary gate electrode layer to have a horizontal plane extending in a plane direction and a vertical plane extending in a height direction (S208), forming a gate insulating layer (S210), forming a preliminary electrode layer on the gate insulating layer, and first patterning the formed preliminary electrode layer to have a horizontal portion extending in the plane direction and a vertical portion extending in the height direction (S212), performing a second patterning of selectively removing only the vertical portion of the horizontal portion and the vertical portion from the first patterned preliminary electrode layer, thereby forming source and drain electrodes (S214), forming a semiconductor layer on the source and drain electrodes and pattering the formed semiconductor layer, thereby forming a vertical channel for connecting the source electrode and the drain electrode in the height direction (S216), and forming a protective layer, forming a contact hole in the protective layer, and then forming a connection electrode in the contact hole (S218).

[0088] Hereinafter, each step will be described in detail. However, for convenience of description, the configuration repeated in the aforementioned manufacturing method according to the first embodiment will be omitted.

[0089] Steps S200, S202, S204, S206, S208, and S210

[0090] In step S200, a substrate 300 may be prepared (see FIG. 23), a lower insulating film 301 may be formed on the substrate (see FIG. 24), and a preliminary gate electrode layer 302 may be formed in step S202 and a hard film 303 may be laminated in step S204 (see FIG. 25). In step S206, a photoresistor 303-1 may be formed (see FIG. 26), the photoresistor 303-1 may be patterned (see FIG. 27), and a hard film 303 may be patterned (see FIG. 28). The patterned remaining photoresistor 303-1 may be removed (see FIG. 29). In step S208, the preliminary gate electrode layer 302 may be patterned as a gate electrode to have a vertical plane through an etching plasma 303-2 (see FIG. 30). In step S210, a gate insulating layer 304 may be formed (see FIG. 31).

[0091] Step S212

[0092] In step S212, a preliminary electrode layer 305 may be formed (see FIG. 32). The preliminary electrode layer may be formed using a sputtering or thermal evaporation scheme. Accordingly, since the preliminary electrode layer is formed in the height direction, the preliminary electrode layer 305 may be formed to be significantly thick in the plane direction parallel to the substrate, and may be formed to be significantly thin in a height direction perpendicular to the substrate.

[0093] Then, the first patterning may be performed so that the preliminary electrode layer 305 has a horizontal portion parallel to the substrate and a vertical portion perpendicular to the substrate by using a photomask process (see FIG. 33).

[0094] Step S214

[0095] In step S214, through the second patterning process, the vertical portion of the first patterned preliminary electrode layer 305 may be removed by using a plasma mode dry etching or wet etching process (305-1) with strong isotropic properties (see FIG. 34). Accordingly, the relatively thin vertical portion of the preliminary electrode layer 305 is removed, so that the source and drain electrodes 306 and 307 may be formed (see FIG. 35). For example, the source electrode 306 may be formed at a height level lower than a height level of the drain electrode 307.

[0096] Step S216

[0097] In step S216, a semiconductor layer 308 may be formed (see FIG. 36). The semiconductor layer 308 may be selectively etched using a photomask process (see FIG. 37). Accordingly, the semiconductor layer may be patterned as a vertical channel 308. According to the second embodiment, the vertical channel 308 is positioned on the source and drain electrodes 306 and 307.

[0098] Step S218

[0099] An upper insulating film 309 may be formed (see FIG. 38). Contact holes 309-1 for contact with the source and drain electrodes may be formed at one side of the upper insulating film 309 (see FIG. 395). Connection electrodes 310 may be formed to electrically come into contact with the source and drain electrodes 306 and 307 through the formed contact holes 309-1, respectively.

[0100] Through the above process, the vertical-structure field-effect transistor 300 according to the second embodiment may be manufactured (see FIG. 40). As previously described with reference to FIG. 1, the at least one of the source and drain electrodes 306 and 307 non-overlaps the gate electrode 302 in the height direction (Y-axis direction of FIG. 40), so that the leakage current and the parasitic capacitance can be minimized.

[0101] Hereinafter, a vertical-structure field-effect transistor 300 according to a third embodiment of the present invention will be described with reference to FIGS. 41 to 58.

[0102] FIGS. 41 and 42 are flowcharts for explaining the method for manufacturing the vertical-structure field-effect transistor according to a third embodiment of the present invention. FIGS. 43 to 58 are views for explaining each step in detail of the method for manufacturing the vertical-structure field-effect transistor according to a third embodiment of the present invention.

[0103] Referring to FIGS. 41 and 42, the vertical-structure field-effect transistor 400 according to a third embodiment of the present invention may include at least one step of: preparing a substrate (S300), forming a preliminary gate electrode layer on the substrate (S302), forming a hard film having an etching rate lower than an etching rate of the gate electrode on the preliminary gate electrode layer (S304), patterning the hard film (S306), using the hard film as a mask and patterning the preliminary gate electrode layer to have a horizontal plane extending in a plane direction and a vertical plane extending in a height direction (S308), forming a gate insulating layer (S310), forming a semiconductor layer on the gate insulating layer, and continuously forming a preliminary electrode layer on the semiconductor layer (S312), forming a vertical channel extending in the height direction by patterning the semiconductor layer with the same mask, and forming the preliminary electrode layer as an intermediate electrode layer having a vertical portion extending in the height direction and a horizontal portion extending in the plane direction (S314), forming source and drain electrodes (S316) by removing the vertical portion of the intermediate electrode layer, and forming a protective layer, forming a contact hole in the protective layer, and then forming a connection electrode in the contact hole (S318).

[0104] Hereinafter, each step will be described in detail. However, for convenience of description, the configurations repeated in the aforementioned manufacturing methods according to the first and second embodiments will be omitted.

[0105] Steps S300, S302, S304, S306, S308, and S310

[0106] In step S300, a substrate 400 may be prepared (see FIG. 43), and a lower insulating film 401 may be formed on the substrate (see FIG. 44). In step S302, a preliminary gate electrode layer 320 may be formed, and in step S304, a hard film 403 may be laminated (see FIG. 45). In step S306, a photoresistor 403-1 may be formed (see FIG. 46), a photoresistor 403-1 may be patterned (see FIG. 47), and the hard film 403 may be patterned (see FIG. 47). The patterned remaining photoresistor 403-1 may be removed (see FIG. 48). In step S308, the preliminary gate electrode layer 402 may be patterned as a gate electrode to have a vertical plane through an etching plasma 403-2 (see FIG. 50). In step S310, a gate insulating layer 404 may be formed (see FIG. 51).

[0107] Step S312

[0108] A semiconductor layer 405 may be formed on the gate insulating layer 404 (see FIG. 52). A preliminary electrode layer 406 may be continuously formed on the semiconductor layer 405 (see FIG. 53). The preliminary electrode layer 406 may be formed by a sputtering process or a thermal evaporation process so that a thickness of the vertical portion is thinner than a thickness of the horizontal portion.

[0109] Step S314

[0110] The semiconductor layer 405 and the preliminary electrode layer 406 may be etched using the same mask (see FIG. 54). Accordingly, the semiconductor layer 405 may be patterned to have a vertical portion. In addition, the preliminary electrode layer 406 may also be patterned as an intermediate electrode layer to have a vertical portion.

[0111] Step S316

[0112] The vertical portion of the intermediate electrode layer 405 may be removed by using a plasma mode dry etching or wet etching process (406-1) with strong isotropic properties (see FIG. 55). This may signify that only the vertical portion can be selectively etched more smoothly because the thickness of the vertical portion of the intermediate electrode layer 405 formed in step S312 is thinner than that of the horizontal portion. Accordingly, source and drain electrodes 407 and 408 may be formed and the source and drain electrodes 407 and 408 may be formed on the vertical channel 405 (see FIG. 56).

[0113] Step S318

[0114] An upper insulating film 409 may be formed (see FIG. 57). Contact holes for contact with the source and drain electrodes may be formed at one side of the upper insulating film 409. Connection electrodes 410 may be formed to electrically come into contact with the source and drain electrodes 407 and 408 through the formed contact holes, respectively (see FIG. 58).

[0115] Through the above process, the vertical-structure field-effect transistor 300 according to the third embodiment may be manufactured (see FIG. 40). As previously described with reference to FIG. 1, the at least one of the source and drain electrodes 407 and 408 non-overlaps the gate electrode 402 in the height direction (Y-axis direction of FIG. 58), so that the leakage current and the parasitic capacitance can be minimized.

[0116] Although the present invention has been described in detail by using exemplary embodiments, the scope of the present invention is not limited to the specific embodiments, and shall be interpreted by the appended claims. In addition, it will be apparent that a person having ordinary skill in the art may carry out various deformations and modifications for the embodiments described as above within the scope without departing from the present invention.