A bidirectional switch element includes: a substrate; an Al.sub.zGa.sub.1-zN layer; an Al.sub.bGa.sub.1-bN layer; a first source electrode; a first gate electrode; a second gate electrode; a second source electrode; a p-type Al.sub.x1Ga.sub.1-x1N layer; a p-type Al.sub.x2Ga.sub.1-x2N layer; an Al.sub.yGa.sub.1-yN layer; and an Al.sub.wGa.sub.1-wN layer. The Al.sub.zGa.sub.1-zN layer is formed over the substrate. The Al.sub.bGa.sub.1-bN layer is formed on the Al.sub.zGa.sub.1-zN layer. The Al.sub.yGa.sub.1-yN layer is interposed between the substrate and the Al.sub.zGa.sub.1-zN layer. The Al.sub.wGa.sub.1-wN layer is interposed between the substrate and the Al.sub.yGa.sub.1-yN layer and has a higher C concentration than the Al.sub.yGa.sub.1-yN layer.

A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a channel layer on the substrate, a first barrier layer on the channel layer, a second barrier layer on the first barrier layer, and a gate element on the second barrier layer. The first barrier layer includes a first material with a first band gap, the second barrier layer includes a second material with a second band gap, and the first band gap is greater than the second band gap.

A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

According to one embodiment, a semiconductor device includes a semiconductor member, a first conductive member, a first electrode, a first insulating member, and a second insulating member. The semiconductor member includes a first partial region, a second partial region, and a third partial region. The first partial region is between the second partial region the third partial region. The first conductive member includes a first conductive portion. The first conductive portion is between the second partial region and the third partial region. The first electrode is electrically connected to the first conductive member. The first electrode includes a first electrode portion, a second electrode portion, and a third electrode portion. The first insulating member includes a first insulating region, a second insulating region, and a third insulating region. The second insulating member includes a first insulating portion and a second insulating portion.

Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

The performance of a transistor is improved. The semiconductor device according to the embodiment includes: an insulating film (12) that separates an n-type transistor formation region (Tr1) and a p-type transistor formation region (Tr2) from each other, in which each of the n-type transistor formation region and the p-type transistor formation region includes a gate electrode (13) formed in a first direction on a semiconductor substrate (11), and source/drain regions (22) formed on both sides of the gate electrode in a second direction different from the first direction, and a distance from an interface between the insulating film and the source/drain regions to an end of the gate electrode in the second direction is different between the n-type transistor formation region and the p-type transistor formation region.

The present application provides a method for preparing a p-type semiconductor structure, an enhancement mode device and a method for manufacturing the same. The method for preparing a p-type semiconductor structure includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer, and at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.

The invention relates to a semiconductor component comprising at least one field effect transistor, said transistor comprising at least a back barrier layer, a buried layer arranged on the back barrier layer, a channel layer arranged on the buried layer, a barrier layer arranged on the channel layer, and a gate layer arranged on the barrier layer, wherein the barrier layer comprises Al.sub.zGa.sub.1-zN and wherein the buried layer comprises Al.sub.xGa.sub.1-xN and at least one dopant causing a p-type conductivity, and wherein the gate layer comprises any of GaN and/or Al.sub.uIn.sub.vGa.sub.1-v-uN. A field effect transistor according to the disclosure may be configured to show a gate threshold voltage which is higher than approximately 0.5 V or higher than approximately 1.0 V.

A semiconductor device includes a semiconductor layer, a first electrode located over the semiconductor layer and connected to the semiconductor layer, a second electrode spaced from the first electrode and located over the semiconductor layer and connected to the semiconductor layer, an insulation film located over the semiconductor layer, and a third electrode interposed between the first electrode and the second electrode, and location over a portion of the insulation film. The insulation film includes a first layer located on the semiconductor layer and between the first electrode and the second electrode and comprising silicon nitride, and a second layer located on the first layer and between the first electrode and the third electrode as well as between the second electrode and the third electrode, and comprising silicon nitride and an amount of oxygen larger than the first layer.