Semiconductor Device

Abstract

The invention relates to a semiconductor component comprising at least one field effect transistor, said transistor comprising at least a back barrier layer, a buried layer arranged on the back barrier layer, a channel layer arranged on the buried layer, a barrier layer arranged on the channel layer, and a gate layer arranged on the barrier layer, wherein the barrier layer comprises Al.sub.zGa.sub.1-zN and wherein the buried layer comprises Al.sub.xGa.sub.1-xN and at least one dopant causing a p-type conductivity, and wherein the gate layer comprises any of GaN and/or Al.sub.uIn.sub.vGa.sub.1-v-uN. A field effect transistor according to the disclosure may be configured to show a gate threshold voltage which is higher than approximately 0.5 V or higher than approximately 1.0 V.

Claims

1. A semiconductor component comprising at least one field effect transistor, said transistor comprising at least a back barrier layer, a buried layer arranged on the back barrier layer, a channel layer arranged on the buried layer, a barrier layer arranged on the channel layer, and a gate layer arranged on the barrier layer, wherein the barrier layer comprises Al.sub.zGa.sub.1-zN, wherein the buried layer comprises Al.sub.xGa.sub.1-xN and at least one dopant causing a p-type conductivity, and the gate layer comprises any of GaN and/or Al.sub.uIn.sub.vGa.sub.1-v-uN.

2. The semiconductor component according to claim 1, wherein the gate layer has a thickness being selected from approximately 10 nm to approximately 100 nm.

3. The semiconductor component according to claim 1, wherein the channel layer has a thickness being selected from approximately 10 nm to approximately 100 nm.

4. The semiconductor component according to claim 1, wherein a concentration of the at least one dopant in the buried layer is selected from approximately 1.Math.10.sup.18 cm.sup.−3 to approximately 2.Math.10.sup.20 cm.sup.−3 and/or wherein the thickness of the buried layer is selected from approximately 20 nm to approximately 150 nm.

5. The semiconductor component according to claim 1, wherein the parameter x is selected from approximately 0.05 to approximately 0.20 and/or wherein the parameter z is selected from approximately 0.20 to approximately 0.35.

6. The semiconductor component according to claim 1, wherein a source and a drain contact are arranged adjacent to the channel layer to define a channel, and a length of the channel between the source and the drain contact is between approximately 1 μm and approximately 50 μm.

7. The semiconductor component according to claim 6, wherein the gate layer is constituted by a partial coating being located between said source and drain contacts.

8. The semiconductor component according to claim 1, wherein a charge carrier density at an interface between the channel layer and the barrier layer is higher than approximately 5.Math.10.sup.12 cm.sup.−2.

9. The semiconductor component according to claim 1, being configured to show a gate threshold voltage which is higher than approximately 0.5 V.

10. The semiconductor component according to claim 1, wherein the gate layer is nominally undoped.

11. The semiconductor component according to claim 1, wherein the buried layer comprises a plurality of individual sublayers each comprising p-doped AlGaN, wherein the aluminum content increases proceeding from the back barrier layer to the channel layer.

12. The semiconductor component according to claim 1, wherein the back barrier layer comprises a p-type dopant, said dopant comprising at least one element from the following list: magnesium, carbon, zinc, and beryllium.

13. The semiconductor component according to claim 1, comprising a first intermediate layer arranged between the back barrier layer and the buried layer comprises or consists of Al.sub.sGa.sub.1-sN or GaN.

14. The semiconductor component according to claim 13, wherein a second intermediate layer is arranged between the channel layer and the buried layer, wherein said second intermediate layer comprises or consists of Al.sub.RGa.sub.1-RN, wherein the parameter R is chosen between 0.05 and 1.

15. The semiconductor component according to claim 1, wherein the channel layer comprises any of nominally undoped GaN or nominally undoped Al.sub.dGa.sub.1-dN.

16. A semiconductor component comprising at least one field effect transistor, said transistor comprising at least a back barrier layer, a buried layer arranged on the back barrier layer, a channel layer arranged on the buried layer, a barrier layer arranged on the channel layer, and a gate layer arranged on the barrier layer, wherein the barrier layer consists of Al.sub.zGa.sub.1-zN, wherein the buried layer comprises Al.sub.xGa.sub.1-xN and at least one dopant causing a p-type conductivity in a concentration of at least 1.Math.10.sup.18 cm.sup.−3 and not more than 2.Math.10.sup.20 cm.sup.−3, and the gate layer consists of any of GaN or Al.sub.uIn.sub.vGa.sub.1-v-uN.

17. The semiconductor component according to claim 16, wherein the gate layer has a thickness being selected from approximately 10 nm to approximately 100 nm.

18. The semiconductor component according to claim 16, wherein the channel layer has a thickness being selected from approximately 10 nm to approximately 100 nm.

19. The semiconductor component according to claim 16, wherein the parameter x is selected from approximately 0.05 to approximately 0.20 and/or wherein the parameter z is selected from approximately 0.20 to approximately 0.35.

20. The semiconductor component according to claim 16, wherein the gate layer is nominally undoped.

21. The semiconductor component according to claim 16, wherein the charge carrier density at the interface between the channel layer and the barrier layer is higher than approximately 5.Math.10.sup.12 cm.sup.−2.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The invention will be explained in greater detail below with reference to exemplary embodiments without restricting the general concept of the invention. The embodiments may be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale. Moreover, in the figures, like-referenced numerals designate corresponding parts throughout the different views.

[0042] FIG. 1 illustrates the basic construction of a semiconductor component according to the invention.

[0043] FIG. 2 illustrates a first exemplary embodiment of the transistor according to the invention.

[0044] FIG. 3 illustrates the calculated band diagram of the gate region of the transistor according to the first exemplary embodiment.

[0045] FIG. 4 illustrates the influence of different doping of the buried layer on the band diagram.

[0046] FIG. 5 illustrates a second exemplary embodiment of the transistor according to the invention.

[0047] FIG. 6 illustrates the calculated band diagram of the gate region of the transistor according to the second exemplary embodiment.

[0048] FIG. 7 illustrates a third exemplary embodiment of the transistor according to the invention.

[0049] FIG. 8 illustrates a fourth exemplary embodiment of the transistor according to the invention.

[0050] FIG. 9 illustrates the calculated band diagram of the gate region of the transistor according to the fourth exemplary embodiment.

[0051] FIG. 10 illustrates a fifth exemplary embodiment of the transistor according to the invention.

[0052] FIG. 11 illustrates the calculated band diagram of the gate region of the transistor according to the fifth exemplary embodiment.

DETAILED DESCRIPTION

[0053] By way of an introductory example, FIG. 1 shows the basic construction of a transistor 1, which may be part of a semiconductor component according to the invention. The transistor 1 may preferably be manufactured by lateral structuring, i.e. as a planar component.

[0054] The transistor 1 may be manufactured together with other parts of the semiconductor component on a substrate 9. In some embodiments of the invention, the substrate may comprise or consist of any of SOI (Silicon-on-insulator) and/or Al.sub.2O.sub.3 and/or SiC and/or Si and/or GaN and/or SiO.sub.2. In some embodiments of the invention the substrate itself may consist of a plurality of individual layers being made from different materials. In some embodiments of the invention, the substrate may be monocrystalline. The substrate may have a diameter of approximately 5 cm to approximately 30 cm or of approximately 10 cm to approximately 20 cm. In some embodiments, the substrate may be removed after the manufacturing of the transistor, for example by etching. In other embodiments of the invention, the substrate may remain below the optional buffer layer 95 in order to facilitate the handling of the transistor in this way.

[0055] Firstly, an optional buffer layer 95 is deposited on the substrate. The deposition of the buffer layer 95 may be carried out from the gas phase by methods known in the art, for example by MBE, MOCVD or MOVPE. The buffer layer 95 may comprise or consist of a binary or ternary or quaternary compound comprising at least one element of main group III and nitrogen. The buffer layer 95 may comprise or consist of a plurality of individual layers. In this case, the composition of the individual layers may change step by step or continuously between the surface of the substrate 9 and the interface of the back barrier layer 2. The buffer layer 95 may be used to reduce the lattice mismatch between the subsequent layers and the substrate 9, such that subsequent layers grow with higher quality and the charge carrier mobility and the threshold voltage rise and the electrical on-resistance decreases as a result. The buffer layer may have a thickness of between approximately 500 nm and approximately 6000 nm. In other embodiments of the invention, the thickness of the back barrier layer may be between 1000 nm and 4000 nm.

[0056] A back barrier layer 2 is subsequently deposited on the substrate 9 or on the buffer layer 95. The deposition of the back barrier layer may be carried out from the gas phase by methods known in the art, for example by MBE, MOCVD or MOVPE. The back barrier layer comprises Al.sub.yGa.sub.1-yN. In some embodiments of the invention, y may be chosen to be between approximately 0.04 and approximately 0.1. if no buffer layer 95 is present, the back barrier layer may be used to reduce the lattice mismatch between the subsequent layers and the substrate. The back barrier layer may have a thickness of between approximately 100 nm and approximately 1000 nm. In other embodiments of the invention, the thickness of the back barrier layer may be between 500 nm and 5000 nm.

[0057] A buried layer 3 is grown onto the back barrier layer. The buried layer 3 comprises Al.sub.xGa.sub.1-xN. In some embodiments of the invention, the parameter x may be chosen to be between approximately 0.05 and approximately 0.15. In addition, the buried layer comprises a dopant that brings about a p-type conductivity of the buried layer. In some embodiments of the invention, the concentration of the dopant may be between approximately 1.Math.10.sup.18 cm.sup.−3 and approximately 2.Math.10.sup.20 cm.sup.−3. The buried layer may have a thickness of approximately 20 nm to approximately 150 nm. The buried layer in interaction with the gate layer 6 generates a piezoelectric field which acts on the material in the channel of the field effect transistor and brings about band bending as a result. As a result, the conduction band minimum can be raised above the Fermi level, such that the transistor has a high resistance or is non-conducting as long as no gate voltage is present at the gate 61. In the event of a gate voltage being applied, the conduction band minimum can be moved below the Fermi level, such that the transistor has a low resistance or becomes conducting. Such behavior is referred to as “normally off” for the purposes of the present invention. The charge carrier density n.sub.s of the conducting transistor may be more than 5.Math.10.sup.12 cm.sup.−2.

[0058] A channel layer 4 is arranged on the buried layer 3 directly or by means of at least one intermediate layer. No intermediate layer is illustrated in FIG. 1. The channel layer 4 may comprise GaN. In other embodiments of the invention, the channel layer 4 may comprise or consist of Al.sub.dGa.sub.1-dN. In some embodiments of the invention, d may be chosen to be between approximately 0.02 and approximately 0.09. In some embodiments of the invention, the channel layer may have a thickness of between approximately 10 nm and approximately 100 nm or between approximately 20 nm and approximately 40 nm.

[0059] Finally, a barrier layer 5 is manufactured on the channel layer 4. Said barrier layer 5 constitutes a Schottky barrier on the channel layer 4. The barrier layer comprises Al.sub.zGa.sub.1-zN. A two-dimensional electron gas forms at the interface 45 between the channel layer 4 and the barrier layer 5. The parameter z may be chosen to be between approximately 0.2 and approximately 0.35. The layer thickness of the barrier layer 5 may be between approximately 5 nm and approximately 20 nm or between approximately 8 nm and approximately 15 nm.

[0060] Finally, a gate layer 6 is manufactured on the barrier layer 5. The gate layer 6 comprises nominally undoped GaN. The gate layer may have a thickness of approximately 20 nm to approximately 40 nm. The gate layer may either be manufactured only on the partial areas of the surface which are provided for receiving the gate electrode 61. Alternatively, the gate layer 6 may be deposited over the whole area and subsequently be at least partly removed from the surface by structuring and etching.

[0061] Finally, a metallic gate electrode 61 is deposited on the gate layer 6. By applying a voltage to the gate electrode 61, it is possible to influence the electrical resistance in the channel between the source electrode 71 and the drain electrode 72, such that the transistor can be used as an amplifier or a switch in a manner known in the art.

[0062] The source and drain electrodes 71 and 72 are also deposited as metal layer onto the barrier layer 5 either directly or with adhesion promoting layers arranged therebetween. The source electrode 71, the drain electrode 72 and/or the gate electrode 61 may be embodied as a multilayer and comprise a plurality of semiconducting or conducting layers composed of metals or alloys. The invention does not teach the use of specific contact materials as a solution principle.

[0063] The subsequent figures show specific embodiments of this general concept of the invention. For reasons of simplification, the substrate 9 and the buffer layer 95 are not illustrated in the subsequent figures. However, these elements may be present in these illustrative embodiments as well.

[0064] FIG. 2 shows one specific exemplary embodiment of the basic structure illustrated in FIG. 1. In the exemplary embodiment illustrated, the back barrier layer 2 has a thickness of 120 nm and an aluminum content of 0.07. The buried layer 3 has a thickness of 80 nm and an aluminum content of 0.12. The buried layer 3 is p-doped and has a charge carrier concentration of 4.Math.10.sup.17 cm.sup.−3. Mg is used as a dopant in the exemplary embodiment illustrated.

[0065] The channel layer comprises nominally undoped GaN with a thickness of 20 nm. A barrier layer having a thickness of 12 nm is deposited thereon, said barrier layer having an aluminum content of 0.26. The gate layer 6 comprises nominally undoped GaN and has a thickness of 15 nm.

[0066] The partial areas not covered by the source, drain and gate electrodes are provided with an optional passivation layer 8, which prevents fluctuation of the surface potential of the barrier layer 5. In the exemplary embodiment illustrated, the passivation layer 8 comprises SiN.

[0067] FIG. 3 shows the calculated band structure of the semiconductor heterostructure under the gate region in accordance with FIG. 2. The calculation is carried out using a one-dimensional, self-consistent Schrödinger-Poisson approach. Energy is plotted against depth in FIG. 3. The illustration shows the profile of the conduction band, of the valence band and the Fermi level. As can be seen from FIG. 3, the conduction band minimum is approximately 0.85 eV above the Fermi level if no gate voltage is present. This means that no free charge carriers are present in the conduction band, such that the semiconductor heterostructure has a comparatively high resistance or is non-conducting. It is only as a result of an electrical voltage being applied to the gate electrode that the Fermi level shifts to an extent such that a two-dimensional electron gas is also formed below the gate electrode. As a result, the conductivity of the channel between source and drain electrodes increases rapidly, such that the transistor is conductive. The transistor according to the invention thus exhibits a normally off behavior.

[0068] FIG. 4 shows the influence of different dopant concentrations of the buried layer on the profile of valence and conduction bands. The illustration shows the profiles of the valence and conduction bands for three values of the charge carrier concentration, namely 2.Math.10.sup.17 cm.sup.−3, 4.Math.10.sup.17 cm.sup.−3 and 6.Math.10.sup.17 cm.sup.−3. As can be seen from FIG. 4, the dopant concentration of the buried layer 3 lifts-up the conduction band profile in the buried layer, and only slightly enhances the band profile between the barrier layer 5 and the channel layer 4. Consequently, all embodiments exhibit a normally off behavior and may yield to a more positive threshold voltage within the increase of the dopant concentration of the buried layer 3.

[0069] A second embodiment of the invention is illustrated with reference to FIG. 5. Like reference numbers designate like parts of the invention, so that the following description is limited to differences between the embodiments shown.

[0070] The second embodiment in accordance with FIG. 5 also uses a back barrier layer 2 having a thickness of 120 nm and an aluminum content of y=0.07. The buried layer 3 arranged thereon has an aluminum content of x=0.12. The dopant concentration is reduced somewhat in comparison with the first embodiment and amounts 3.Math.10.sup.17 cm.sup.−3. The layer thickness of the buried layer 3 is likewise reduced in comparison with the first embodiment and is approximately 65 Nm.

[0071] A channel layer 4 made from AlGaN having a thickness of 25 nm and an aluminum content of 4% is arranged on the buried layer. A barrier layer 5 is deposited on the channel layer 4, having a thickness of 25 nm and an aluminum content of 26% as described above. A gate layer 6 made from nominally undoped GaN is situated below the gate electrode 61, said gate layer having a layer thickness of 15 nm.

[0072] FIG. 6 shows the calculated band diagram of the second embodiment of the invention below the gate. In this case, too, the conduction band minimum is above the Fermi level if no gate voltage is present at the gate electrode 61. The separation between the conduction band minimum and the Fermi energy with a value of 1.0 eV is somewhat greater than that determined for the first exemplary embodiment.

[0073] The charge carrier density at the interface 45 is 8.3.Math.10.sup.12 cm.sup.−2. This value, too, is slightly greater than in the first exemplary embodiment, in which the charge carrier density is 7.5.Math.10.sup.12 cm.sup.−2.

[0074] FIG. 7 shows a third embodiment of the present invention. For reasons of simplification, the source, drain and gate contacts are not illustrated in FIG. 7. They can be realized in a similar manner than described with respect to the previous embodiments by partly removing the gate layer 6 and providing the free surface regions with corresponding contact elements.

[0075] The third embodiment of the invention is distinguished by the fact that at least one first intermediate layer is arranged between the back barrier layer and the buried layer 3. In the exemplary embodiment illustrated, the first intermediate layer is constructed from a three-layered layer system comprising a first individual layer 31, a second individual layer 32 and a third individual layer 33. In this case, the first and third individual layers comprise Al.sub.sGa.sub.1-sN and Al.sub.TGa.sub.1-TN, respectively. The aluminum content S and T of the first intermediate layer 31 and of the third intermediate layer 33 may vary.

[0076] In some embodiments of the invention, the parameters s and t may be chosen to be between 0.09 and 0.15. The layer thicknesses of the single individual layer 31, 32 and 33 may be between approximately 5 nm and approximately 15 nm.

[0077] A second individual layer 32, which comprises or consists of GaN, is arranged between the first individual layer 31 and the third individual layer 33. The intermediate layers can amplify the field induced by the polarization and, as a result, either raise the threshold voltage further and/or further improve the confinement of the two-dimensional electron gas at the interface 45 between channel layer and barrier layer.

[0078] The number of individual layers in the multilayer system forming the first intermediate layer may be greater or less than is illustrated in FIG. 7 and may be between 1 and approximately 20, for example. In other embodiments of the invention, the number of individual layers may be between two and five. The invention does not teach the use of exactly three individual layers as a solution principle.

[0079] FIG. 7 furthermore shows an optional second intermediate layer 41, which comprises or consists of Al.sub.rGa.sub.1-rN. The latter may be arranged between the buried layer 3 and the channel layer 4. In some embodiments of the invention, the layer thickness may be between approximately 2 nm and approximately 30 nm. The aluminum content r may be between approximately 0.05 and 1. This second intermediate layer 41, too, may be constituted as a layer system composed of a plurality of individual layers that are deposited epitaxially one above another.

[0080] A calculation of the band structure of the semiconductor structure illustrated in FIG. 7 likewise shows that the conduction band minimum is above the Fermi level, such that the semiconductor structure shown in FIG. 7 is suitable for producing a transistor having normally off behavior.

[0081] A fourth embodiment of the invention is explained with reference to FIG. 8. The fourth embodiment of the invention exhibits a buried layer 3 comprising a plurality of individual layers 21, 22 and 23. The number of individual layers is not fixed at exactly three. Rather, this number may be greater or else smaller and be between approximately 2 and approximately 30, for example. The individual layers 21, 22, . . . may have a thickness of 2 to 10 nm, for example.

[0082] Each individual layer comprises p-doped Al.sub.xGa.sub.1-xN. In this case, the dopant just like the aluminum content X may be chosen differently in different individual layers. In some embodiments of the invention, the aluminum content may increase proceeding from the back barrier layer 2 to the channel layer 4.

[0083] FIG. 9 shows the calculated band diagram of the semiconductor structure illustrated in FIG. 8. Here, too, it becomes clear that the conduction band minimum is above the Fermi level, such that the semiconductor structure is suitable for producing a normally off transistor.

[0084] FIG. 10 shows a fifth embodiment of the present invention. The fifth embodiment is similar to the third embodiment illustrated in FIG. 7, and so the following description is restricted to the essential differences.

[0085] The fifth embodiment of the invention is also distinguished by the fact that a second intermediate layer 41 is arranged between the channel layer 4 and the buried layer 3, said second intermediate layer comprising or consisting of Al.sub.rGa.sub.1-rN. In some embodiments of the invention, the layer thickness may be between approximately 10 nm and approximately 30 nm. The aluminum content r may be between approximately 0.1 and 0.30. In the case of the fifth embodiment of the invention, however, no first intermediate layer is situated between the back barrier layer 2 and the buried layer 3.

[0086] A calculated band structure of the fifth embodiment of the semiconductor structure according to the invention is illustrated with reference to FIG. 11. As can be seen from FIG. 11, in this case, too, the conduction band minimum is above the Fermi level, such that the semiconductor structure shown in FIG. 10 is likewise suitable for producing a transistor having normally off behavior. The potential well formed by the conduction band is 1.28 eV above the Fermi level, thus resulting in a distinctly positive threshold voltage of the transistor. The potential profile nevertheless enables a good confinement of the two-dimensional electron gas.

[0087] The calculated charge carrier density of the transistor in accordance with the fifth embodiment is 9.5.Math.10.sup.12 cm.sup.−2

[0088] To summarize, the invention discloses for the first time semiconductor structures which can be used to provide field effect transistors having threshold voltages of more than 0.5 V or more than 0.85 V or more than 1.0 V. The present invention thus discloses for the first time field effect transistors which combine the advantageous properties of components on the basis of group III nitrides with the advantages of normally off transistors and at the same time have a threshold voltage which is controllable in a simple manner and thus requires only a low circuit complexity.

[0089] It should be emphasized that the invention is not restricted to the embodiments illustrated. Therefore, the above description should not be regarded as restrictive, but rather as explanatory. The following claims should be understood such that a feature mentioned is present in at least one embodiment of the invention. This does not preclude the presence of further features. In so far as the claims and the above description define “first” and “second” elements or “first” and “second” embodiments, this designation serves for differentiating between two embodiments or elements of the same type, without defining a rank order.