Example embodiments relate to field-effect transistors. An example field-effect transistor includes a plurality of field-effect transistor elements, each field-effect transistor element including a gate finger and a gate runner. The gate finger of each field-effect transistor element is electrically connected at a plurality of spaced apart positions to the gate runner of that element. Each gate finger is made of a first material or material composition and has a first electrical resistivity. The field-effect transistor further includes, for each gate finger, a gate resistor through which the electrical connection between the gate finger and the gate runner at a position among the plurality of spaced apart positions is realized. The gate resistor is made of a second material or material composition and has a second electrical resistivity that is higher than the first electrical resistivity.

A gate pad includes a first portion disposed in a gate pad region and a second portion continuous with the first portion and disposed in a gate resistance region. The gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer provided on a front surface of a semiconductor substrate via a gate insulating film is disposed between the semiconductor substrate and an interlayer insulating film, has a surface area that is at least equal to a surface area of the gate pad, and faces the gate pad in a depth direction. The gate polysilicon layer has a planar outline similar to that of the gate pad and includes continuous first and second portions, the first portion facing the first portion of the gate pad overall, and a second portion facing the second portion of the gate pad.

A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.

A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.

Field-effect transistors (FETs) are described that comprise a semiconducting gate (SG) layer, referred to herein as SG-FETs. In one or more embodiments, the FETs can include a channel layer and a SG layer capacitively coupled to the channel layer. The SG layer has an embedded voltage-clamping function that provides internal gate over voltage protection without an additional protection circuit. The embedded voltage-clamping function is based on the SG layer having a maximum effective gate voltage that is clamped to the depletion threshold of the SG layer.

The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

A semiconductor device and methods of fabricating and using the same are provided. The semiconductor device comprises a channel region and at least a first, second, and third electrode. The channel region includes a compound having a transition metal and a chalcogen. The thickness of the channel region is about 3 to about 40 atomic layers.

A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.

The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

In an edge termination region, a second gate runner for a current sensor is formed between a first gate runner for a main semiconductor device and an active region. The second gate runner surrounds the periphery of the active region in a substantially rectangular shape having an opening. One end of the second gate runner is connected to all of the gate electrodes of the current sensor, and the other end is connected to the first gate runner at between a gate pad and an OC pad. This makes it possible to increase the gate capacitance of the current sensor as the current sensor switches ON and OFF when a pulse-shaped gate voltage is applied to the gate pad by an amount proportional to the surface area of the second gate runner.