A method of restricting diffusion of miscible materials across a barrier, including, forming a 2-dimensional material on a substrate surface, wherein the 2-dimensional material includes one or more defects through which a portion of the substrate surface is exposed, forming a plug selectively on the exposed substrate surface, and forming a cover layer on the plug and 2-dimensional material, wherein the cover layer material is miscible in the substrate material.

A method of making an array of sensor pixels, the method comprising: forming an array of nucleation sites on a growth substrate, each nucleation site configured to facilitate the growth of a respective domain of channel material on the growth substrate, the array of nucleation sites having a predefined configuration corresponding to an arrangement of pixel regions on a target substrate; growing an array of domains of channel material on the growth substrate from the array of respective nucleation sites to form a layer of channel material; and transferring the layer of channel material onto the target substrate such that the domains of channel material are substantially aligned with the pixel regions of the target substrate to allow the formation of a pixel array, each pixel of the array comprising source and drain electrodes configured to enable a flow of electrical current through a respective domain of channel material, and a functionalising material on the domain of channel material configured to produce a detectable change in the flow of electrical current on exposure to a physical stimulus which is indicative of one or more of the presence and magnitude of the physical stimulus.

A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.

A method for manufacturing a graphite layer on an interstitial carbide layer, includes depositing a metal layer formed by one or more metals on a carbide substrate, the metal layer being able to form an interstitial carbide, the metal layer at least partially covering the carbide substrate; performing a heat treatment during which a temperature higher than the dissociation temperature of the carbide of the carbide substrate is applied; wherein the heat allows a reaction between the metal layer and the carbide substrate to form the interstitial carbide layer as well as a first part of the graphite layer at the surface of the interstitial carbide layer, and, when the metal layer only partially covers the carbide substrate, a formation of a second part of the graphite layer at the surface of the carbide substrate which is not covered with the metal layer.

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same materialgraphene.

A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of the method, the substrate equipped with the 2D layered semiconductor is exposed to a reaction gas, and a stimulus is applied to the reaction gas to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants can be decomposed and removed. Additionally, the contaminants can be removed without damage to the 2D layered semiconductor. A functional layer is in-situ deposited to be in contact with the 2D layered semiconductor. Without the contaminants, a clean interface between the functional layer and the 2D layered semiconductor can be obtained and the 2D layered semiconductor can exhibit better electrical properties.

The present invention relates to a method for connecting an electrical contact to a nanomaterial carried by a substrate. At least one layer of soluble lithography resist is provided on the nanomaterial. An opening in the at least one layer of resist exposes a surface portion of the nanomaterial. At least a portion of the exposed surface portion of the nanomaterial is removed to thereby expose the underlying substrate and an edge of the nanomaterial. A metal is deposited on at least the edge of the nanomaterial and the exposed substrate such that the metal forms an electrical contact with the nanomaterial. Removing at least a portion of the soluble lithography resist from the nanomaterial such that at least a portion of the two-dimensional material is exposed.

Hot metal dissolution of carbon atoms is used to structure a diamond substrate. A layer of catalytic material is deposited on at least a portion of a surface of the diamond substrate. The layer of catalytic material may be structured using photolithography to define a gap exposing the surface of the diamond substrate, where the gap has a (110) orientation relative to the crystal structure of the diamond substrate. The exposed surface of the diamond substrate is etched to form at least one recess having at least one (111) oriented diamond surface (facet). The catalytic material is removed by a suitable cleaning process. The (111) oriented surface is then overgrown with diamond comprising a dopant resulting in a conductivity of the overgrown diamond that is different from the conductivity of the doped substrate. The doping concentration of the overgrown diamond is greater than 10.sup.19 cm.sup.3.

A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of the method, the substrate equipped with the 2D layered semiconductor is exposed to a reaction gas, and a stimulus is applied to the reaction gas to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants can be decomposed and removed. Additionally, the contaminants can be removed without damage to the 2D layered semiconductor. A functional layer is in-situ deposited to be in contact with the 2D layered semiconductor. Without the contaminants, a clean interface between the functional layer and the 2D layered semiconductor can be obtained and the 2D layered semiconductor can exhibit better electrical properties.

A method of restricting diffusion of miscible materials across a barrier, including, forming a 2-dimensional material on a substrate surface, wherein the 2-dimensional material includes one or more defects through which a portion of the substrate surface is exposed, forming a plug selectively on the exposed substrate surface, and forming a cover layer on the plug and 2-dimensional material, wherein the cover layer material is miscible in the substrate material.