A semiconductor device may include an n type layer sequentially disposed at a first surface of an n+ type silicon carbide substrate; a p type region disposed in the n type layer; an auxiliary n+ type region disposed on the p type region or in the p type region; an n+ type region disposed in the p type region; an auxiliary electrode disposed on the auxiliary n+ type region and the p type region; a gate electrode separated from the auxiliary electrode and disposed on the n type layer; a source electrode separated from the auxiliary electrode and the gate electrode; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the auxiliary n+ type region and the n+ type region are separated from each other, and the source electrode is in contact with the n+ type region.

A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.

A buffer layer is employed to fabricate diamond membranes and allow reuse of diamond substrates. In this approach, diamond membranes are fabricated on the buffer layer, which in turn is disposed on a diamond substrate that is lattice-matched to the diamond membrane. The weak bonding between the buffer layer and the diamond substrate allows ready release of the fabricated diamond membrane. The released diamond membrane is transferred to another substrate to fabricate diamond devices, while the diamond substrate is reused for another fabrication.

Semiconductor devices including two-dimensional (2D) materials and methods of manufacturing the semiconductor devices are provided. A semiconductor device may include a semiconductor layer including layers of a 2D material, and an intercalation material between the layers of the 2D material. The semiconductor device may further include a first conductive layer on a first surface of the semiconductor layer and a second conductive layer on a second surface of the semiconductor layer that is opposite the first surface. A portion of the 2D material may have a first crystalline structure, and another portion of the 2D material may have a second crystalline structure that is different from the first crystalline structure. The 2D material may include a metal chalcogenide-based material.

A pressure sensing device having a Dirac material and a method of operating the same are provided. The pressure sensing device includes a Dirac material pattern disposed on a substrate and having a band structure in which Dirac cones meet at a Dirac point. A source electrode and a drain electrode are respectively connected to the Dirac material pattern. A spacer layer including a cavity on the Dirac material pattern is disposed on the substrate. A gate electrode overlapping the Dirac material pattern is disposed on the cavity.

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same materialgraphene.

A patterning method of a graphene, including a step of forming a graphene layer on a polymer substrate; and a step of forming a nanopattern in the graphene layer by hot embossing imprinting. The step of forming a nanopattern in the graphene layer by hot embossing imprinting includes contacting a hot mold, in which a nanopattern is formed, or contacting a roll-to-roll hot mold, in which a nanopattern is formed, to the graphene layer, followed by heating and pressing the graphene layer. In the step of forming a nanopattern in the graphene layer, the graphene layer is cleaved by a protrusion of the nanopattern formed on the hot mold or the hot roll-to-roll mold, and the cleaved graphene is present on each of a protrusion and a recessed portion of the nanopattern formed in the polymer substrate under the graphene later.

A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.

A method for manufacturing a graphite layer on an interstitial carbide layer, includes depositing a metal layer formed by one or more metals on a carbide substrate, the metal layer being able to form an interstitial carbide, the metal layer at least partially covering the carbide substrate; performing a heat treatment during which a temperature higher than the dissociation temperature of the carbide of the carbide substrate is applied; wherein the heat allows a reaction between the metal layer and the carbide substrate to form the interstitial carbide layer as well as a first part of the graphite layer at the surface of the interstitial carbide layer, and, when the metal layer only partially covers the carbide substrate, a formation of a second part of the graphite layer at the surface of the carbide substrate which is not covered with the metal layer.

Non-conductive substrates, especially the sidewalls of micro/nano holes thereof are chemically modified (i.e., chemically grafted) by reduced graphene oxide (rGO). The rGO possesses excellent electrical conductivity and therefore the modified substrates become conductive, so that it can be directly electroplated. These rGO-grafted holes can pass thermal shock reliability test after electroplating. The rGO grafting process possesses many advantages, such as a short process time, no complex agent (i.e., no chelator), no toxic agents (i.e., formaldehyde for electroless Cu deposition). It is employed in an aqueous solution instead of an organic solvent, and therefore is environmentally friendly and beneficial for industrial production.