A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.

A semiconductor memory device and a method of fabrication of the same are provided. The semiconductor memory device comprises a two-terminal memory cell sequentially joined together with a first high concentration doping region doped with a first conductive dopant, a second base region doped with a second conductive type dopant, a first base region doped with the first conductive type dopant, and a second high concentration doping region doped with the second conductive type dopant, wherein a write voltage of the memory cell is controlled by adjusting the lengths or doping concentrations of the first and second base regions.

A method for regulating, with a computer, a resistive element arranged to deice and/or demist a support, the method including: a) a loop for monitoring the temperature T and the moisture level H at the support; b) a deicing and/or demisting sequence which, as long as the temperature T and the moisture level H monitored by the monitoring loop a) are indicative of an absence of frost or mist on the support, keeps the resistive element inactive and, in the contrary case, demands, in a step b2), the circulation of a current I in the resistive element so that the latter dissipates a thermal power P.sub.th, adjusted according to the temperature T and the moisture level H, and providing deicing or demisting of the support over a predetermined period D.sub.p.

A two-terminal memory device includes: a substrate; an extended drain extending from a drain and a lower surface of the drain and laminated on the substrate; a ferroelectric layer connected to the drain and covering the extended drain and the substrate; and a source laminated on the ferroelectric layer to face the drain.

A method for manufacturing a two-terminal memory device includes: forming an extended drain and a drain layer on a substrate; forming a ferroelectric layer covering the substrate and the extended drain; forming a semiconducting layer on the ferroelectric layer, and forming a source layer connected to the semiconducting layer on the ferroelectric layer.

Embodiments of the invention are directed to an integrated circuit (IC) that includes a stacked device configuration having a top electronic device positioned over a bottom electronic device, along with an isolation region operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device. The gate region of the top electronic device includes a first conductive material, and the gate region of the bottom electronic device includes a second conductive material that is different from the first conductive material.

Disclosed are an integrate-and-fire neuron circuit implemented to enable an integrate-and-fire operation with only a small number of devices by using bistable resistance characteristics of the same two heterojunction NPN devices, unlike a CMOS-based integrate-and-fire neuron circuit having a complex structure, and an operation method thereof. In one or more aspects, an integrate-and-fire neuron circuit and an operation method thereof can increase neuron integration in a system by implementing an integrate-and-fire operation of neurons using only three transistors and two capacitors, or two transistors, one resistor and one capacitor, can improve the efficiency of spiking neural network learning by controlling a fire threshold point of neurons through regulation of a gate voltage of the same two NPN devices, and can expect an increase in energy efficiency of the entire system through inhibition of excessive fire by implementing excitatory and inhibitory post-synaptic potentials.

There is provided a non-volatile memory device comprising: a substrate; a lower electrode disposed on the substrate; a resistance layer disposed on the lower electrode; and an upper electrode disposed on the resistance layer, wherein the resistance layer include a stack of a graphene oxide film and an iron oxide film, wherein a resistance value of the resistance layer varies based on a voltage applied to the upper electrode.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains and surface charges in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields and surface charges can control the structural phase of the two-dimensional material, which in turn determines whether the two-dimensional material layer is insulating or metallic, has a band gap or no band gap, and whether it is magnetic or non-magnetic. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

A semiconductor memory device and a method of fabrication of the same are provided. The semiconductor memory device comprises a two-terminal memory cell sequentially joined together with a first high concentration doping region doped with a first conductive dopant, a second base region doped with a second conductive type dopant, a first base region doped with the first conductive type dopant, and a second high concentration doping region doped with the second conductive type dopant, wherein a write voltage of the memory cell is controlled by adjusting the lengths or doping concentrations of the first and second base regions.