Disclosed is a method for manufacturing an ESD protection device. The ESD protection device includes a rectifier diode and an open-base bipolar transistor, the anode of the rectifier diode is the first doped region and the cathode of the rectifier diode is the semiconductor substrate, the emitter region, base region and collector region of the open-base bipolar transistor are the second doped region, the epitaxial semiconductor layer and semiconductor substrate, respectively, the first doped region and the second doped region extend through the doped region into the epitaxial semiconductor layer by a predetermined depth. The doped region can suppress the induced doped region around the second doped region, so that the parasitic capacitance of the open-base bipolar transistor is reduced and the response speed is improved.

A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.

A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.

A method of operating a bipolar transistor having a source, a drain, and a channel electrically coupled to the source and the drain includes applying a bias voltage to a gate electrically coupled to the channel, increasing a conductivity of the channel via field ionization in response to applying the bias voltage, and conducting current from the source to the drain

Provided are a lateral p-n junction black phosphorus thin film, and a method of manufacturing the same, and specifically, a lateral p-n junction black phosphorus thin film in which a p-type black phosphorus thin film having a p-type semiconductor property and a n-type black phosphorus thin film having a n-type semiconductor property form a lateral junction by modifying some regions on a surface of the black phosphorus thin film through light irradiation with a compound having a specific chemical structure, and a method of manufacturing the same.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains and surface charges in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields and surface charges can control the structural phase of the two-dimensional material, which in turn determines whether the two-dimensional material layer is insulating or metallic, has a band gap or no band gap, and whether it is magnetic or non-magnetic. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

A phase-change memory cell, comprising: a substrate housing a transistor, for selection of the memory cell, that includes a first conduction electrode; a first electrical-insulation layer on the selection transistor; a first conductive through via through the electrical-insulation layer electrically coupled to the first conduction electrode; a heater element including a first portion in electrical contact with the first conductive through via and a second portion that extends in electrical continuity with, and orthogonal to, the first portion; a first protection element extending on the first and second portions of the heater element; a second protection element extending in direct lateral contact with the first portion of the heater element and with the first protection element; and a phase-change region extending over the heater element in electrical and thermal contact therewith.

Apparatus and other embodiments associated with high speed and high breakdown voltage rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in ring shape enclosed a vertical P-N junction. For each deep trench, a corresponding wider ring-shape P+ region is created on top of a N epi layer. This enclosed deep trench surrounding a vertical P-N junction and a thinner N epitaxial layer allow higher reverse bias voltage and low leakage current. In another embodiment, an enclosed deep trench in ring shape surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. The structure can be extended to multiple deep trenches with associated horizontal P-N junctions. In a further embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create yet another device with very high breakdown voltage and very low leakage current. This structure can be extended to multiple deep trenches and shallow trenches as well.