A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.

A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material-string constructions that extend through the insulative tiers and the conductive tiers into the conductor tier. The channel material of the channel-material-string constructions directly electrically couples to conductor material of the conductor tier. The conductor tier comprises islands comprising material of different composition from that of the conductor material of the conductor tier that surrounds individual of the islands. The islands are directly against bottoms of the channel-material-string constructions. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other aspects, including method, are disclosed.

A semiconductor memory device includes a discharge contact passing through a source structure, a gate stack disposed on a partial region of the source structure, a vertical structure passing through the gate stack, and an insulating pattern passing through the source structure between the vertical structure and the discharge contact.

Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.

A semiconductor device according to an embodiment includes a first conductive layer extending like a plate in a first direction; a second conductive layer extending like a plate in a second direction intersecting the first direction; and a first memory film arranged in such a manner as to be sandwiched between the first conductive layer and the second conductive layer in a third direction intersecting the first direction and the second direction in a region where the first conductive layer and the second conductive layer intersect, wherein a memory cell is configured in an arc shape in the region where the first conductive layer and the second conductive layer intersect using a part of the first conductive layer, a part of the first memory film, and a part of the second conductive layer.

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.

An apparatus includes: a semiconductor substrate; an isolation region in the semiconductor substrate, the isolation region including an isolation trench filled with an insulating material therein; a plurality of island-shaped active regions in the semiconductor substrate surrounded by the isolation region; and a buried word-line having a bottom, the buried word-line at least passing across the isolation region between the plurality of active regions; wherein the isolation trench includes upper, middle and lower portions, each of the upper and lower portions has a substantially flat surface and the middle portion has a bulged surface.

A memory device and a method of manufacturing the memory device includes a stacked structure having a cell region and a slimming region. The memory device also includes a plurality of vertical channel structures each including memory cells and vertically passing through the stacked structure in the cell region. The memory device further includes a plurality of support structures each having a structure of each of the vertical channel structures and vertically passing through the stacked structure in the slimming region. The plurality of support structures have different heights depending on the shape of the stacked structure in the slimming region.