According to one embodiment, a semiconductor memory device includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked; and a pillar including a channel layer extending in a stacking direction of the plurality of conductive layers in the stacked body, a memory layer provided on a side surface of the channel layer, and a cap layer provided on the channel layer, the cap layer being connected to an upper layer wiring of the stacked body, wherein the channel layer extends into the stacked body at least from a height position of an uppermost conductive layer of the plurality of conductive layers, and a grain size of crystal contained in the channel layer is larger than a grain size of crystal contained in the cap layer.

A semiconductor storage device according to an embodiment includes a stacked body and a pillar. The pillar includes an insulating core, a channel layer, and a memory film. A plurality of gate electrode layers included in the stacked body includes a plurality of first gate electrode layers and one or more second gate electrode layers. The channel layer includes a first portion and a second portion. The first portion is provided between an uppermost first gate electrode layer and the insulating core. The second portion extends from a first height to a second height. A film thickness of the second portion is greater than a film thickness of the first portion.

A semiconductor memory device includes a substrate, a semiconductor layer extending in a first direction, a first conductive layer extending in a second direction and opposed to the semiconductor layer, an electric charge accumulating layer disposed between the semiconductor layer and the first conductive layer, and a first contact electrode extending in the first direction and connected to the first conductive layer. The first contact electrode has one end in the first direction farther from the substrate than the first conductive layer, the other end in the first direction closer to the substrate than the first conductive layer. The first conductive layer includes a first part opposed to the semiconductor layer and a second part connected to the first contact electrode. The second part has a thickness in the first direction larger than a thickness in the first direction of the first part.

A semiconductor device is provided. The semiconductor device includes a metal-oxide-semiconductor field-effect-transistor (MOSFET) device electrically attachable to a first data line and a read-only memory (ROM) element. The ROM element is electrically interposable between the MOSFET device and a second data line. The ROM element includes first and second sets of memory cells in high and low resistance states, respectively, to form a secure identifier (ID).

A semiconductor storage device includes conductive layers and inter-layer insulating layers alternately arranged over a substrate having a first region and a second region arranged in a first direction; and a first structure provided in a second region of the substrate. The first structure includes: a plurality of third regions provided at first positions corresponding to at least some of the plurality of conductive layers, respectively, and a plurality of fourth regions provided at second positions corresponding to at least some of the plurality of inter-layer insulating layers, respectively. A first width of the plurality of third regions in the first direction is greater than a second width of the plurality of fourth regions in the first direction.

A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.

A semiconductor memory device includes a substrate including a first region and a second region, a plurality of first conductive layers, a first semiconductor layer disposed in the first region, an electric charge accumulating layer, a contact electrode disposed in the second region and connected to one of the plurality of first conductive layers, and a plurality of first structures and a plurality of second structures disposed in the second region. The first structure includes a second semiconductor layer opposed to the plurality of first conductive layers and including a semiconductor material in common with the first semiconductor layer, and a first insulating layer disposed between the plurality of first conductive layers and the second semiconductor layer and including an insulating material in common with the electric charge accumulating layer. The second structure does not include the semiconductor material or the insulating material.

Provided is a three-dimensional flash memory including a substrate, a stack structure, a stop layer, two slit trenches, a plurality of vertical channel structures, and a plurality of slit holes. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The stop layer is disposed between the substrate and the stack structure. The two slit trenches penetrate through the stack structure to expose the stop layer. The vertical channel structures are disposed between the two slit trenches and penetrate through the stack structure and the stop layer. The slit holes are discretely disposed between the vertical channel structures, and penetrate through the stack structure to expose the stop layer. A method of forming the three-dimensional flash memory is also provided.

A semiconductor device of an embodiment includes a semiconductor layer, a gate electrode layer, and a first insulating layer provided between the semiconductor layer and the gate electrode layer, the first insulating layer including aluminum oxide including at least one crystal phase selected from the group consisting of alpha (α)-aluminum oxide and theta (θ)-aluminum oxide, the first insulating layer having a thickness of equal to or less than 2.5 nm in a first direction from the semiconductor layer toward the gate electrode layer.

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.