An apparatus and method for generating an electrical circuit of semiconductor channel resistor including a first passive element part including a resistor and a capacitor connected in parallel between a first port and a second port, and an ohmic resistor connected in series to the resistor and the capacitor which are connected in parallel are provided. The apparatus includes a substrate selection part configured to receive a selected substrate item; a resistor selection part configured to receive a selected resistor item; a capacitor selection part configured to receive a selected capacitor item; and a circuit generating part configured to generate an electrical circuit from the selected substrate item, the selected resistor item, and the selected capacitor item.

A field-effect transistor with protection diodes includes: a field-effect transistor; and a two-terminal electrostatic protection circuit connected between a gate and a source of the field-effect transistor, wherein the two-terminal electrostatic protection circuit comprises: a first diode that is positioned on a reverse-biased side when a voltage lower than a potential of the source is applied to the gate and has a reverse withstand voltage lower than a reverse withstand voltage between the gate and the source of the field-effect transistor; a second diode that is positioned on a forward-biased side when a voltage lower than a potential of the source is applied to the gate and is connected in anti-series to the first diode; and a resistor that is connected in series to a diode pair comprising the first diode and the second diode and formed using a same channel layer as that of the field-effect transistor.

A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

A light emitting component includes plural transfer elements, plural setting thyristors, and plural light emitting elements. The transfer elements are configured to be sequentially brought into an ON state. The setting thyristors are connected to the transfer elements, respectively. The setting thyristors are configured to be brought into a state where the setting thyristors are capable of changing to the ON state when the transfer elements are brought into the ON state. The light emitting elements are stacked on the setting thyristors through tunnel junctions, respectively. The light emitting elements are configured to emit light of increase a light emission amount when the setting thyristors are brought into the ON state.

This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator adjacent to the resistor, removing the barrier, and forming a gate layer on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.

An electronic device can include a substrate defining a trench. In an embodiment, a semiconductor body can be within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate. In an embodiment, an electronic component can be within the semiconductor body. The electronic component can be a resistor or a diode. In a particular embodiment, the semiconductor body has an upper surface, the electronic component is within and along an upper surface and spaced apart from a bottom of the semiconductor body. In a further embodiment, the electronic device can further include a first electronic component within an active region of the substrate, an isolation structure within the trench, and a second electronic component within the isolation structure.

An electronic device can include a substrate defining a trench. In an embodiment, a semiconductor body can be within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate. In an embodiment, an electronic component can be within the semiconductor body. The electronic component can be a resistor or a diode. In a particular embodiment, the semiconductor body has an upper surface, the electronic component is within and along an upper surface and spaced apart from a bottom of the semiconductor body. In a further embodiment, the electronic device can further include a first electronic component within an active region of the substrate, an isolation structure within the trench, and a second electronic component within the isolation structure.

We disclose a Ill-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor (19) formed on a substrate, the first heterojunction transistor comprising: a first Ill-nitride semiconductor region formed over the substrate, wherein the first Ill-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal (8) operatively connected to the first Ill-nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first Ill-nitride semiconductor region; a first gate terminal (10) formed over the first Ill-nitride semiconductor region between the first terminal and the second terminal. The device also includes a second heterojunction transistor (14) formed on a substrate, the second heterojunction transistor comprising: a second Ill-nitride semiconductor region formed over the substrate, wherein the second Ill-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a third terminal operatively connected to the second Ill-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second Ill-nitride semiconductor region, wherein the fourth terminal is operatively connected to the first gate terminal; and a second gate terminal formed over the second Ill-nitride semiconductor region between the third terminal and the fourth terminal and wherein the second heterojunction transistor is used in sensing and protection functions of the first power heterojunction transistor. The device also includes at least one monolithically integrated current sensing transistor (16) that has a substantially identical structure to the first heterojunction transistor, and

wherein the third transistor is scaled to a smaller area or a shorter gate width when compared to the first heterojunction transistor by a scale factor, X, where X is larger than 1. Other embodiments include both internal and external sensing, sensing loads and a feedback circuit to provide overcurrent, gate over-voltage or over-temperature protection.

An electronic device can include a drain terminal, a control terminal, and a source terminal, a first HEMT, and a second HEMT. The first HEMT can include a drain electrode coupled to the drain terminal, a gate electrode coupled to the first control terminal, and a source electrode coupled to the source terminal. The second HEMT can include a drain electrode, a gate electrode, and a source electrode. The drain electrode can be coupled to the drain terminal, and the source electrode can be coupled to the source terminal. In an embodiment, a resistor can be coupled between the gate and source electrodes of the second HEMT, and in another embodiment, the gate electrode of the second HEMT can electrically float. During or after a triggering event, the second HEMT can turn on temporarily to divert some of the charging from the triggering event into the second HEMT.