A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region.

A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region.

A method for manufacturing a three-dimensional semiconductor diode device comprises providing a substrate comprising a silicon substrate and a first oxide layer formed on the silicon substrate; depositing a plurality of stacked structures on the substrate, each of the stacked structures comprising a dielectric layer and a conductive layer; etching the stacked structures through a photoresist layer which is patterned to form at least one trench in the stacked structures, a bottom of the trench exposing the first oxide layer; depositing a second oxide layer on the stacked structures and the trench; depositing a high-resistance layer on the second oxide layer, the high-resistance layer comprising a first polycrystalline silicon layer and a first conductive compound layer; and depositing a low-resistance layer on the high-resistance layer, the low-resistance layer comprising a second polycrystalline silicon layer and a second conductive compound layer.

A method for manufacturing a three-dimensional semiconductor diode device comprises providing a substrate comprising a silicon substrate and a first oxide layer formed on the silicon substrate; depositing a plurality of stacked structures on the substrate, each of the stacked structures comprising a dielectric layer and a conductive layer; etching the stacked structures through a photoresist layer which is patterned to form at least one trench in the stacked structures, a bottom of the trench exposing the first oxide layer; depositing a second oxide layer on the stacked structures and the trench; depositing a high-resistance layer on the second oxide layer, the high-resistance layer comprising a first polycrystalline silicon layer and a first conductive compound layer; and depositing a low-resistance layer on the high-resistance layer, the low-resistance layer comprising a second polycrystalline silicon layer and a second conductive compound layer.

An electrostatic discharge (ESD) protection device including: a substrate including: a first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region has a first conductivity type and a first doping concentration and the first and third doped regions have a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; and a doped island region disposed within the second doped region, the first and second doped terminal regions and doped island region have the second conductivity type and a third doping concentration, the third doping concentration higher than the first and second doping concentrations; and conductive terminals respectively coupled to the doped terminal regions; and an insulation layer arranged on the substrate between the conductive terminals and covering at least the second doped region.

An electrostatic discharge (ESD) protection device including: a substrate including: a first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region has a first conductivity type and a first doping concentration and the first and third doped regions have a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; and a doped island region disposed within the second doped region, the first and second doped terminal regions and doped island region have the second conductivity type and a third doping concentration, the third doping concentration higher than the first and second doping concentrations; and conductive terminals respectively coupled to the doped terminal regions; and an insulation layer arranged on the substrate between the conductive terminals and covering at least the second doped region.

A semiconductor device includes a main element and a sense element. Each of the main element and the sense element includes a drift layer, a base layer, an emitter region, a gate insulation film, a gate electrode, and a rear surface layer. The base layer is on the drift layer. The emitter region is at a surface layer portion of the base layer. The gate insulation film is disposed at a surface of the base layer between the emitter region and the drift layer. The gate electrode is on the gate insulation film. The rear surface layer faces the base layer with the drift layer between the rear surface layer and the base layer. The rear surface layer in the main element includes a collector layer. The rear surface layer in the sense element includes a low-impurity layer having smaller amount of impurities than the collector layer.

The present disclosure provides a diode-triggered bidirectional silicon controlled rectifier and circuit. The silicon controlled rectifier includes: a P-type substrate; a first P well formed in the P-type substrate, a first P-type doped region and a first N-type doped region being formed in the first P well; a second P well formed in the P-type substrate, a third N-type doped region and a fourth P-type doped region being formed in the second P well; and an N well formed in the P-type substrate, a second P-type doped region, a second N-type doped region and a third P-type doped region being formed in the N well. The second N-type doped region is electrically connected with a positive electrode of a diode string, and the first P-type doped region and the fourth P-type doped region are electrically connected with a negative electrode of the diode string.