A High Mobility Electron Transistor (HEMT) and a capacitor co-formed on an integrated circuit (IC) share at least one structural feature, thereby tightly integrating the two components. In one embodiment, the shared feature may be a 2DEG channel of the HEMT, which also functions in lieu of a base metal layer of a conventional capacitor. In another embodiment, a dialectic layer of the capacitor may be formed in a passivation step of forming the HEMT. In another embodiment, a metal contact of the HEMT (e.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor. In these embodiments, one or more processing steps required to form a conventional capacitor are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT.

A High Mobility Electron Transistor (HEMT) and a capacitor co-formed on an integrated circuit (IC) share at least one structural feature, thereby tightly integrating the two components. In one embodiment, the shared feature may be a 2DEG channel of the HEMT, which also functions in lieu of a base metal layer of a conventional capacitor. In another embodiment, a dialectic layer of the capacitor may be formed in a passivation step of forming the HEMT. In another embodiment, a metal contact of the HEMT (e.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor. In these embodiments, one or more processing steps required to form a conventional capacitor are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT.

A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

Systems and methods related to a parametric amplifier including a quantum capacitor are described. In one example, a parametric amplifier comprising an input terminal for receiving a qubit signal is provided. The parametric amplifier further includes a pump terminal for receiving a pump signal. The parametric amplifier further comprises an amplifier, including a plurality of quantum capacitance devices configured to operate in a cryogenic environment, configured to amplify the qubit signal by mixing the qubit signal with the pump signal to generate an amplified signal. The parametric amplifier further includes an output terminal for providing the amplified signal.

A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.

A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.

A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.

NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.

NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.