In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns.

A solar cell apparatus 100 and a method for forming said solar cell apparatus 100, comprising a substrate 101, a n-type transparent conductive oxide (TCO) layer 102 deposited atop said substrate 101, a p-i-n structure 200 that includes a p-type layer 103, an i-type layer 104, a n-type layer 105, a metal back layer 106 deposited atop said n-type layer 105 of the p-i-n structure 200. The n-type layer 105 comprises n-type donors 115 including phosphorus atoms. The n-type donors 115 include oxygen atoms at an atomic concentration comprised between 5% and 25% of the overall atomic composition of the n-type layer 105.

A process for preparing a passivated emitter rear contact solar cell, which includes the steps as follows: removing the damaged layer on the surface of the silicon wafer and at the same time polishing both surfaces, texturing, forming PN junction, etching, removing the glass impurity, depositing a passivation film on the back surface, depositing a passivating antireflective layer on the front surface, making local openings on the back surface, screen printing of metal paste on both the front surface and the back surface and sintering, in which the texturing step employs a catalytic metal etching approach, and the textured structure is a nanometer-level textured structure. The present invention has combined removing the damaged layer on the surface of the silicon wafer and polishing both the front and back surfaces into one single step, and thus has simplified the production process and reduced the production cost.

In a method of manufacturing a solar cell, a groove is formed on a first surface of an n-type semiconductor substrate. A p-side transparent conductive film layer is formed on the first surface of the n-type semiconductor substrate formed with the groove. A non-deposition area, where the p-side transparent conductive film layer is not formed, is formed in at least a part of a side surface of the groove formed on the first surface of the n-type semiconductor substrate.

Photovoltaic structures are disclosed. The structures can comprise randomly or periodically structured layers, a dielectric layer to reduce back diffusion of charge carriers, and a metallic layer to reflect photons back towards the absorbing semiconductor layers. This design can increase efficiency of photovoltaic structures. The structures can be fabricated by nanoimprint.

Methods of patterning a layer of a photonic device are provided using stamps or masks derived from pre-written optical media discs. One method comprises pressing a stamp on a surface of a layer of a photonic device, the stamp comprising a stamping surface which defines a negative replica of a quasi-random pattern of nanostructures defined in a recording layer of a pre-written optical media disc, for a period of time sufficient to imprint the quasi-random pattern of nanostructures defined in the recording layer of the pre-written optical media disc onto the surface of the layer of the photonic device; and removing the stamp. The stamps, the masks, and the photonic devices comprising the patterned layers are also provided.

High speed optoelectronic devices and associated methods are provided. In one aspect, for example, a high speed optoelectronic device can include a silicon material having an incident light surface, a first doped region and a second doped region forming a semiconductive junction in the silicon material, and a textured region coupled to the silicon material and positioned to interact with electromagnetic radiation. The optoelectronic device has a response time of from about 1 picosecond to about 5 nanoseconds and a responsivity of greater than or equal to about 0.4 A/W for electromagnetic radiation having at least one wavelength from about 800 nm to about 1200 nm.

The invention relates to a semiconductor device, e.g. for the emission or absorption of light, preferably in the deep ultraviolet (DUV) range. The device, e.g. a resonant cavity light emitting diode (RCLED) or a laser diode, is formed from: a substrate layer (302), preferably comprising a distributed Bragg reflector (DBR); a graphitic layer (304); and at least one semiconductor structure (310), preferably a wire or a pyramid, grown on the graphitic layer, with or without the use of a mask layer (306). The semiconductor structure is constructed from at least one III-V semiconductor n-type doped region (316) and a hexagonal boron-nitride (hBN) region (312), preferably being p-type doped hBN.

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region. Metallization methods, include etching techniques for forming a first and second conductive contact structure are also described.

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.