A semiconductor device includes: a conductive layer; a plurality of nanopillars spaced apart from each other overlying the conductive layer, each nanopillar comprising a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer being different in conductivity type from the second semiconductor layer; and a graphene layer overlying the plurality of nanopillars, the graphene layer being connected to each of the plurality of nanopillars.

A front electrode layer of a thin film solar cell is provided. The front electrode layer includes a first transparent conductive layer and a second transparent conductive layer. The first transparent conductive layer is disposed on a substrate, and the second transparent conductive layer is disposed on the first transparent conductive layer, wherein the first transparent conductive layer is located between the substrate and the second transparent conductive layer, and wherein a surface roughness of the second transparent conductive layer is lower than a surface roughness of the first transparent conductive layer.

A solar cell and a solar laminate are described. The solar cell can have a front side which faces the sun during normal operation and a back side opposite front side. The solar cell can include conductive contacts having substantially reflective outer regions disposed on the back side of the solar cell. The solar laminate can include a first encapsulant, the first encapsulant disposed on the back side of the solar cell and a second encapsulant. The solar laminate can include the solar cell laminated between the first and second encapsulant. The substantially reflective outer regions of the conductive contacts and the first encapsulant can be configured to scatter and/or diffuse light at the back side of the solar laminate for substantial light collection at the back side of the solar cell. Methods of fabricating the solar cell are also described herein.

An optical sensor includes a substrate, a first/second/third well disposed in a sensing region, a deep trench isolation structure, and a passivation layer. The substrate has a first conductivity type and includes the sensing region. The first well has a second conductivity type and a first depth. The second well has the second conductivity type and a second depth. The third well has the first conductivity type and a third depth. The deep trench isolation structure is disposed in the substrate and surrounding the sensing region, wherein the depth of the deep trench isolation structure is greater than the first depth, the first depth is greater than the second depth, and the second depth is greater than the third depth. The passivation layer is disposed over the substrate, wherein the passivation layer includes a plurality of protruding portions disposed directly above the sensing region.

A semiconductor-based sensor with enhanced light absorption, and in particular, enhanced infrared light absorption includes a semiconductor light sensor element and a patterned spatially inhomogeneous dielectric layer disposed over the semiconductor light sensor element. Characteristically, spatial inhomogeneity of the patterned spatially inhomogeneous dielectric layer is optimized to provide a maximized electric field in the semiconductor light sensor element such light absorption is enhanced.

Provided is a texture structure manufacturing method with which a texture structure can be obtained simply. The texture structure manufacturing method comprises: growing a layer including a randomly distributed nanostructure on a major surface of a base material; forming a light-scattering body having the nanostructure embedded therein; and exposing a surface of the light-scattering body by removing a part or all of the base material and the layer including the nanostructure.

A {100} indium phosphide (InP) wafer has multiplies of olive-shaped etch pits on the back side surface of the wafer, wherein the olive shape refers to a shape with its both ends being narrow and its middle being wide, e.g., an oval shape. A method of manufacturing the {100} indium phosphide wafer comprises: etching the wafer by immersing it into an etching solution to produce etch pits; washing the wafer with deionized water; protecting the back side surface of the wafer; mechanical polishing and chemical polishing the front side surface of the wafer, and then washing it with deionized water; de-protecting the back side surface of the wafer; wherein the etching solution comprises an acidic substance, deionized water and an oxidizing agent. The wafer can be heated uniformly during the epitaxial growth and thus displays good application effect.

Discloses is a method of manufacturing a solar cell with an increased power generation area to increase the area used for actual power generation without increasing the size of the solar cell.

A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.

The present invention relates to a solar cladding member comprising a solar power module, the solar power module encapsulated in a polymeric material and comprising a first surface arranged to be exposed to sunlight in use and an opposing surface affixed to a substrate. An electrical junction is configured to connect the solar power module to an electrical system for transfer of electrical power from the solar power module, the electrical junction located on the opposing surface of the solar power module adjacent the substrate. The substrate comprises a cavity facing the opposing surface of the solar power module, the cavity bounded by the substrate, and configured to accommodate and seal the electrical junction therein.