The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a fin-type active region extruded from a semiconductor substrate; a gate stack disposed on the fin-type active region; a source/drain feature formed in the fin-type active region and disposed on a side of the gate stack; an elongated contact feature landing on the source/drain feature; and a dielectric material layer disposed on sidewalls of the elongated contact feature and free from ends of the elongated contact feature.

A solid-state imaging device includes a photoelectric conversion unit, a transistor, and an element separation region separating the photoelectric conversion unit and the transistor. The photoelectric conversion unit and the transistor constitute a pixel. The element separation region is formed of a semiconductor region of a conductivity type opposite to that of a source region and a drain region of the transistor. A part of a gate electrode of the transistor protrudes toward the element separation region side beyond an active region of the transistor. An insulating film having a thickness substantially the same as that of a gate insulating film of the gate electrode of the transistor is formed on the element separation region continuing from a part thereof under the gate electrode of the transistor to a part thereof continuing from the part under the gate electrode of the transistor.

An image sensor includes: a light receiving section suitable for generating photocharges in response to incident light; and a driving section including a source follower transistor suitable for generating an output voltage corresponding to a reference voltage in response to the photocharges. The source follower transistor includes: a stack structure formed by sequentially stacking a first conductive layer, an insulating layer and a second conductive layer; an open portion formed through the second conductive layer and the insulating layer so as to expose the first conductive layer; a channel layer formed along the surface of the open portion so as to be connected to the first conductive layer and the second conductive layer; and a gate is connected to the light receiving section and which is formed over the channel layer so as to overlap the second conductive layer.

A SJ-MOSFET includes a parallel pn layer in which an n-type drift region and a p-type partition region are alternately arranged repeatedly along a direction parallel to a base main-surface. The n-type drift region and the p-type partition region have total impurity amounts that are roughly the same and widths that are basically constant over an entire depth direction. The n-type drift region is configured to have an n-type impurity concentration profile in which an impurity concentration of a portion on the drain-side is higher than an impurity concentration of a portion on the source-side by C.sub.nx. The p-type partition region is configured to have a p-type impurity concentration profile in which an impurity concentration of a portion on the drain-side is higher than an impurity concentration of a portion on the source-side by C.sub.ph, and an impurity concentration of part of the portion on the source-side is relatively low.

A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric capacitor formed thereon.

A semiconductor device formed on a semiconductor substrate, comprising: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region; and an island region under the contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer. The active region comprises: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench.

A solid-state imaging device includes a plurality of photoelectric conversion units, a floating diffusion unit that is shared by the plurality of photoelectric conversion units and converts electric charge generated in each of the plurality of photoelectric conversion units into a voltage signal, a plurality of transfer units that are respectively provided in the plurality of photoelectric conversion units and transfer the electric charge generated in the plurality of photoelectric conversion units to the floating diffusion unit, a first transistor group that is electrically connected to the floating diffusion unit and includes a gate and source/drain which are arranged with a first layout configuration, and a second transistor group that is electrically connected to the floating diffusion unit, includes a gate and source/drain arranged with a second layout configuration symmetrical to the first layout configuration, and is provided in a separate area from the first transistor group.

A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines includes a resistance section formed of a locally increased specific resistance relative to a specific resistance of adjacent semiconductor material or metal of the respective connection line. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.

A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.