A semiconductor device includes a gate structure, a double diffused region, a source region, a drain region, a first gate spacer, and a second gate spacer. The gate structure is over a semiconductor substrate. The double diffused region is in the semiconductor substrate and laterally extends past a first side of gate structure. The source region is in the semiconductor substrate and is adjacent a second side of the gate structure opposite the first side. The drain region is in the double diffused region in the semiconductor substrate and is of a same conductivity type as the double diffused region. The first gate spacer is on the first side of the gate structure. The second gate spacer extends upwardly from the double diffused region along an outermost sidewall of the first gate spacer and terminates prior to reaching a top surface of the gate structure.

A semiconductor structure and method of manufacturing a semiconductor structure are provided. The method includes receiving a substrate with fin features; forming sacrificial gate stacks over the substrate; forming a sacrificial fill layer over the sacrificial gate stacks; removing the sacrificial fill layer; forming sidewall spacers besides the sacrificial gate stacks; removing the sacrificial gate stacks; and forming metal gate stacks; wherein the sacrificial fill layers is made of fill materials with a high etch rate selectivity to materials of the sidewall spacers.

Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes providing a substrate including a first region and a second region, and forming a plurality of fins over the first region. The method also includes forming an isolation layer over a front surface of the substrate, and forming a power rail opening by etching the isolation layer and a first portion of the second region. In addition, the method includes forming a through-hole by etching a second portion of the substrate, and forming a first metal layer in the power rail opening and the through-hole. Further, the method includes thinning a back surface of the substrate until the first metal layer is exposed, and back-etching the back surface of the substrate to enable a back surface of the first metal layer to be above the back surface of the substrate.

An electromagnetic wave detector includes: an insulating film having a first surface and a second surface facing the first surface; a first layer to perform photoelectric conversion by an incident electromagnetic wave and change in potential, the first layer being made of a first two-dimensional atomic layer material; and a second layer to receive the change in potential through the first insulating film and generate change in electrical quantity, the second layer being made of a second two-dimensional atomic layer material and provided on the first surface. In this manner, the sensitive electromagnetic wave detector detecting an incident electromagnetic wave as change in electrical quantity and having high response speed to an incident electromagnetic wave can be provided.

Systems and methods of the disclosed embodiments include a semiconductor device having a semiconductor substrate. The semiconductor substrate has a first major surface, an opposing second major surface, a first doped region of a first conductivity type disposed beneath the first major surface, and a semiconductor region of the first conductivity type disposed between the first doped region and the second major surface. The semiconductor device may also include a trench isolation structure, comprising a conductive trench filling enclosed by an insulating trench liner. The trench isolation structure extends from the first major surface through the first doped region and into the semiconductor region. The semiconductor device may also include a semiconductor device structure disposed with a drain structure, and a connection structure formed between the conductive trench filling of the trench isolation structure and the drain region.

A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.