Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.

An image sensing device is disclosed. The image sensing device includes a semiconductor substrate including an active region, a first impurity region and a second impurity region formed in the active region, a photoelectric conversion region disposed over the semiconductor substrate to be directly coupled to the first impurity region and configured to generate photocharges in response to incident light and transmit the generated photocharges to the first impurity region, a switching element disposed coupled to the first impurity region and the second impurity region and configured to transmit the photocharges stored in the first impurity region to the second impurity region, an insulation structure disposed on sides of the photoelectric conversion region and a plurality of conductive lines disposed in the insulation structure and configured to read out an electrical image signal corresponding to the photocharges generated by the photoelectric conversion region.

A method for fabricating an image-sensor chip-scale package includes bonding, with temporary adhesive, a glass wafer to a device wafer including an array of image sensors. The method also includes forming an isolated-die wafer by removing, from the device wafer, each of a plurality of inter-sensor regions each located between a respective pair of image sensors of the array of image sensors. The isolated-die wafer includes a plurality of image-sensor dies each including a respective image sensor, of the array of image sensors, bonded to the glass wafer. The method also includes encapsulating the isolated-die wafer to form an encapsulated-die wafer; removing, from each of the plurality of image-sensor dies, a respective region of the glass wafer covering the respective image sensor; and singulating the encapsulated-die wafer.

High performance single crystal silicon cells and arrays thereof are manufactured using a rapid process flow. Tunneling junctions formed in the process provide performance benefits, such as higher efficiency and a lower power temperature coefficient. The process generates a large array of interconnected high performance cells smaller than typical cells without requiring additional process steps, and simplifies integration of these coupons into the final product. The cells can have different shapes, sizes, and orientations, enabling the array to be flexible in any desired direction. Higher efficiencies and lower hot spotting under shading is achieved by connecting small low current, high voltage cells in dense series and parallel configurations. Low current cells also require much less metallization than typical solar cells and arrays.

High performance single crystal silicon cells and arrays thereof are manufactured using a rapid process flow. Tunneling junctions formed in the process provide performance benefits, such as higher efficiency and a lower power temperature coefficient. The process generates a large array of interconnected high performance cells smaller than typical cells without requiring additional process steps, and simplifies integration of these coupons into the final product. The cells can have different shapes, sizes, and orientations, enabling the array to be flexible in any desired direction. Higher efficiencies and lower hot spotting under shading is achieved by connecting small low current, high voltage cells in dense series and parallel configurations. Low current cells also require much less metallization than typical solar cells and arrays.

A buried word line structure including a substrate, an isolation structure, and a buried word line is provided. The isolation structure is located in the substrate to define active regions separated from each other. The active regions extend in a first direction. The buried word line is located in the substrate. The buried word line extends through the isolation structure and the active regions in a second direction. The first direction intersects the second direction. The buried word line and the substrate are isolated from each other. The same buried word line includes a first portion and a second portion. The first portion is located in the active regions. The second portion is located in the isolation structure between two adjacent active regions in the first direction. A width of the first portion is greater than a width of the second portion.

An image sensor and a method for fabricating the image sensor are provided. In the method for fabricating the image sensor, at first, a substrate having a first surface and a second surface opposite to the first surface is provided. Then, light-sensitive regions are formed in the substrate. Thereafter, transfer gate structures are formed on the first surface of the substrate. Then, the first surface of the substrate is formed to form recess structures on the light-sensitive regions. Thereafter, light-reflective layers are formed to cover the recess structures of the first surface of the substrate, in which the recess structures are filled with protrusion structures of the light-reflective layers. Further, the second surface of the substrate may be etched to form recess structures corresponding to the light-sensitive regions.

The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

A display device includes: a substrate including a display area and a non-display area; a gate driver disposed on the substrate in the non-display area and including a plurality of stages that generate a gate signal and output the gate signal to the display area; a switching transistor and a driving transistor disposed on the substrate in the display area; and a light emitting diode connected to the driving transistor, wherein each of the plurality of stages may include a plurality of transistors, wherein a channel layer of the driving transistor includes a first oxide semiconductor material, and a channel layer of the plurality of transistors included in each of the plurality of stages includes a second oxide semiconductor material, wherein the first oxide semiconductor material is different from the second oxide semiconductor material, and wherein the second oxide semiconductor material may include tin.

An image sensor may include a substrate including a plurality of unit pixel regions and having first and second surfaces facing each other. Each of the unit pixel regions may include a plurality of floating diffusion parts spaced apart from each other in the substrate, storage nodes provided in the substrate to be spaced apart from and facing the floating diffusion parts, a transfer gate adjacent to a region between the floating diffusion parts and the storage nodes, and photoelectric conversion parts sequentially stacked on one of the first and second surfaces. Each of the photoelectric conversion parts may include common and pixel electrodes respectively provided on top and bottom surfaces thereof and each pixel electrode may be electrically connected to a corresponding one of the storage nodes.