A heterojunction device is provided. The heterojunction device includes a silicon (Si) substrate; and a film of silicon carbide (SiC) deposited on a surface of the Si substrate. The SiC has a Si:C ratio that increases or decreases from a SiC surface in contact with the Si substrate to an opposing SiC surface that is not in contact with the Si substrate.

The present disclosure falls into the field of optoelectronics, particularly, includes the design, epitaxial growth, fabrication, and characterization of Laser Diodes (LDs) operating in the ultraviolet (UV) to infrared (IR) spectral regime on patterned substrates (PSs) made with (formed on) low cost, large size Si, or GaN on sapphire, GaN, and other wafers. We disclose three types of PSs, which can be universal substrates, allowing any materials (III-Vs, II-VIs, etc.) grown on top of it with low defect and/or dislocation density.

A laser-assisted microfluidics manufacturing process has been developed for the fabrication of additively manufactured structures. Roll-to-roll manufacturing is enhanced by the use of a laser-assisted electrospray printhead positioned above the flexible substrate. The laser electrospray printhead sprays microdroplets containing nanoparticles onto the substrate to form both thin-film and structural layers. As the substrate moves, the nanoparticles are sintered using a laser beam directed by the laser electrospray printhead onto the substrate.

An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. The configuration of the dielectric structures and the photosensitive material promote total internal reflection of light within a passivation layer.

A method of growing fully relaxed SiGeSn buffer layers on Si substrates to produce virtual substrates for the epitaxial growth of high quality GeSn films suitable for high performance infrared (IR) optoelectronic device technology directly integrated on silicon. Growing the SiGeSn virtual substrate uses a precisely decreasing growth temperature and Si flux and a precisely increasing Ge and Sn flux. The virtual substrates may have a slightly larger lattice constant than that of the target GeSn alloy to impose a precise degree of tensile strain resulting in a direct band gap for the target GeSn alloy.

An optical device for detecting a first chemical species and a second chemical species contained in a specimen, which includes: a first optical sensor, which may be optically coupled to an optical source through the specimen and is sensitive to radiation having a wavelength comprised in a first range of wavelengths; and a second optical sensor, which may be optically coupled to the optical source through the specimen and is sensitive to radiation having a wavelength comprised in a second range of wavelengths, different from the first range of wavelengths.

A Dense Wavelength Division Multiplexing (DWDM) photonic integration circuit (PIC) that implements a DWDM system, such as a transceiver, is described. The DWDM PIC architecture includes photonic devices fully integrating on a single manufacturing platform. The DWDM PIC has a multi-wavelength optical laser, a quantum dot (QD) laser with integrated heterogeneous metal oxide semiconductor (H-MOS) capacitor, integrated on-chip. The multi-wavelength optical laser can be a symmetric comb laser that generates two equal outputs of multi-wavelength light. Alternatively, the DWDM PIC can be designed to interface with a stand-alone multi-wavelength optical laser that is off-chip. In some implementations, the DWDM PIC integrates multiple optimally designed photonic devices, such as a silicon geranium (SiGe) avalanche photodetector (APD), an athermal H-MOS wavelength splitter, a QD photodetector, and a heterogenous grating coupler. Accordingly, fabricating the DWDM PIC includes a unique III-V to silicon bonding process, which is adapted for its use of SiGe APDs.

One illustrative photodiode disclosed herein includes an N-doped anode region, a P-doped cathode region and at least one P-doped charge region positioned laterally between the N-doped anode region and the P-doped cathode region. In this example, the photodiode also includes a plurality of quantum dots embedded within the at least one P-doped charge region and an N-doped impact ionization region positioned laterally between the N-doped anode region and the at least one P-doped charge region.

Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.

Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.