Patent classifications
H01L31/1832
Electromagnetic radiation detector based on wafer bonding
Monolithic pixel detectors, systems and methods for the detection and imaging of electromagnetic radiation with high spectral and spatial resolution comprise a Si wafer with a CMOS processed pixel readout bonded to an absorber wafer in wafer bonds comprising conducting bonds between doped, highly conducting charge collectors in the readout and highly conducting regions in the absorber wafer and poorly conducting bonds between regions of high resistivity.
CdSeTe PHOTOVOLTAIC DEVICES WITH INTERDIGITATED BACK CONTACT ARCHITECTURE
Disclosed herein are CdSeTe photovoltaic devices having interdigitated back contact architecture for use in polycrystalline thin films in photovoltaic devices.
SEMICONDUCTOR WAFER, RADIATION DETECTION ELEMENT, RADIATION DETECTOR, AND PRODUCTION METHOD FOR COMPOUND SEMICONDUCTOR MONOCRYSTALLINE SUBSTRATE
Provided is a CdZnTe monocrystalline substrate which has a small leakage current even when a voltage is applied from a low voltage to a high voltage, and which has a lower variation in resistivity with respect to applied voltage changes from 0 to 900 V, and which can maintain a stable resistivity. A semiconductor wafer comprising a cadmium zinc telluride monocrystal having a zinc concentration of 4.0 at % or more and 6.5 at % or less and a chlorine concentration of 0.1 ppm by weight or more and 5.0 ppm by weight or less, wherein when a voltage is applied in a range of from 0 to 900 V, the semiconductor wafer has a resistivity for each applied voltage value of 1.0×10.sup.7 Ωcm or more and 7.0×10.sup.8 Ωcm or less, and wherein a relative variation coefficient of each resistivity to the applied voltages in a range of from 0 to 900 V is 100% or less.
Using a compliant layer to eliminate bump bonding
Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.
Copper-based chalcogenide photovoltaic device and a method of forming the same
A method for forming a photovoltaic device comprising the steps of: providing a first conductive material on a substrate; depositing a continuous layer of a dielectric material less than 10 nm thick on the first conductive material; annealing the first conductive material and the layer of dielectric material; forming a chalcogenide light-absorbing material on the layer of dielectric material; and depositing a second material on the light-absorbing material such that the second material is electrically coupled to the light-absorbing material; wherein the first conductive material and the dielectric material are selected such that, during the step of annealing, a portion of the first conductive material undergoes a chemical reaction to form: a layer of a metal chalcogenide material at the interface between first conductive material and the dielectric material; and a plurality of openings in the layer of dielectric material; the openings being such to allow electrical coupling between the light-absorbing material and the layer of a metal chalcogenide material. Additionally contemplated is a photovoltaic device formed by this method.
Radiation detecting element and method for producing radiation detecting element
Provided is a radiation detecting element that has high adhesion between electrode portions and a substrate and does not suffer from performance failures due to insufficient insulation between the electrode portions, even if a distance between the electrode portions is narrower in order to obtain a high-definition radiation drawn image. The radiation detecting element includes: a plurality of electrode portions; and an insulating portion provided between the electrode portions on a surface of a substrate made of a compound semiconductor crystal containing cadmium telluride or cadmium zinc telluride, wherein an intermediate layer containing tellurium oxide is present between each of the electrode portions and the substrate, and wherein tellurium oxide is present on an upper portion of the insulating portion, and the tellurium oxide on the upper portion of the insulating portion has a maximum thickness of 30 nm or less.
Photovoltaic device including a p-n junction and method of manufacturing
A photovoltaic device includes a substrate structure and a p-type semiconductor absorber layer. A photovoltaic device may include a CdSeTe layer. A process for manufacturing a photovoltaic device includes forming a CdSeTe layer over a substrate. The process includes forming a p-type cadmium selenide telluride absorber layer.
Dual band photodiode element and method of making the same
Mercury cadmium telluride (MCT) dual band photodiode elements are described that include an n-type barrier region interposed between first and second p-type regions. The first p-type region is arranged to absorb different IR wavelengths to the second p-type region in order that the photodiode element can sense two IR bands. A portion of the second p-type region is type converted using ion-beam milling to produce a n-type region that interfaces with the second p-type region and the n-type barrier region.
USING A COMPLIANT LAYER TO ELIMINATE BUMP BONDING
Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.
Photovoltaic devices and method of making
Embodiments of a photovoltaic device are provided herein. The photovoltaic device can include a layer stack and an absorber layer disposed on the layer stack. The absorber layer can include a first region and a second region. Each of the first region of the absorber layer and the second region of the absorber layer can include a compound comprising cadmium, selenium, and tellurium. An atomic concentration of selenium can vary across the absorber layer. The first region of the absorber layer can have a thickness between 100 nanometers to 3000 nanometers. The second region of the absorber layer can have a thickness between 100 nanometers to 3000 nanometers. A ratio of an average atomic concentration of selenium in the first region of the absorber layer to an average atomic concentration of selenium in the second region of the absorber layer can be greater than 10.