A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer.

Methods of fabricating solar cells having junctions retracted from cleaved edges, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface, a back surface, and sidewalls. An emitter region is in the substrate at the light-receiving surface of the substrate. The emitter region has sidewalls laterally retracted from the sidewalls of the substrate. A passivation layer is on the sidewalls of the emitter region.

An electrical device includes an aluminum nitride passivation layer for a mercury cadmium telluride (Hg.sub.1-xCd.sub.xTe) (MCT) semiconductor layer of the device. The AlN passivation layer may be an un-textured amorphous-to-polycrystalline film that is deposited onto the surface of the MCT in its as-grown state, or overlying the MCT after the MCT surface has been pre-treated or partially passivated, in this way fully passivating the MCT. The AlN passivation layer may have a coefficient of thermal expansion (CTE) that closely matches the CTE of the MCT layer, thereby reducing strain at an interface to the MCT. The AlN passivation layer may be formed with a neutral inherent (residual) stress, provide mechanical rigidity, and chemical resistance to protect the MCT.

The present disclosure provides a method for rapidly treating a heterojunction solar cell fabricated using a crystalline silicon wafer doped exclusively with n-type dopants to improve surface passivation and carrier transport properties using the following steps: providing a heterojunction solar cell; the solar cell having an n-type silicon substrate exclusively doped with n-type dopants with a concentration higher than 1×10.sup.14 cm.sup.−3 and a plurality of metallic contacts; illuminating a surface portion of the solar cell for a period of less than 5 minutes and at a temperature between 200° C. and 300° C. with light having an intensity of at least 2 kW/m.sup.2 and a wavelength such that the light is absorbed by the surface portion and generates electron-hole pairs in the solar cell. The step of illuminating a surface portion of the solar cell is such that less than 0.5 kWh/m.sup.2 of energy is transferred to the surface portion and a temperature of the surface portion increases at a rate of at least 10° C./s for a period of time during illumination.

Photovoltaic devices with very high breakdown voltages are described herein. Typical commercial silicon photovoltaic devices have breakdown voltages below 50-100 volts (V). Even though such devices have bypass diodes to prevent photovoltaic cells from going into breakdown, the bypass diodes have high failure rates, leading to unreliable devices. A high-efficiency silicon photovoltaic cell is provided with very high breakdown voltages. By combining a device architecture with very low surface recombination and silicon wafers with high bulk resistivity (above 10 ohms centimeter (Ω-cm)), embodiments described herein achieve breakdown voltages close to 1000 V. These photovoltaic cells with high breakdown voltages improve the reliability of photovoltaic devices, while reducing their design complexity and cost.

A photovoltaic device is described, the device comprising a transparent conducting electrode layer; a back contact layer comprising at least one MXene material; and an active layer, comprising a photovoltaic active material, disposed between the transparent conducting electrode layer and the back contact layer. Also described is a method of producing a photovoltaic device, the method comprising the steps of providing substrate, depositing a transparent conducting electrode over the substrate; depositing an active layer comprising a photovoltaic material over the transparent conducting electrode; and depositing an MXene layer material over the active layer. A method of generating electricity using the disclosed device is also described.

Methods of fabricating solar cells having junctions retracted from cleaved edges, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface, a back surface, and sidewalls. An emitter region is in the substrate at the light-receiving surface of the substrate. The emitter region has sidewalls laterally retracted from the sidewalls of the substrate. A passivation layer is on the sidewalls of the emitter region.

A solar cell can include a silicon semiconductor substrate; an oxide layer on a first surface of the silicon semiconductor substrate; a polysilicon layer on the oxide layer; a diffusion region at a second surface of the silicon semiconductor substrate; a dielectric film on the polysilicon layer; a first electrode connected to the polysilicon layer through the dielectric film; a passivation film on the diffusion region; and a second electrode connected to the diffusion region through the passivation film.

A tandem solar cell includes a perovskite solar cell including a perovskite absorption layer, a silicon solar cell placed under the perovskite solar cell, a junction layer placed between the perovskite solar cell and the silicon solar cell, an upper electrode placed on the perovskite solar cell, and a lower electrode placed under the silicon solar cell.

Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and a one-dimensional size of the top surface of the outermost first substructure is less than or equal to 45 μm; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer, the doped conductive layer includes a P-type doped conductive layer and an N-type doped conductive layer; and a second passivation layer located on a surface of the doped conductive layer.