Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask. The mask includes a pattern defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate. The patterning the substrate includes anisotropically removing portions of the substrate exposed by the plurality of spaces.

An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.

Provided are a HJT cell having high photoelectric conversion efficiency and a method for preparing the same. The HJT cell includes an N-type crystalline silicon wafer. An intrinsic amorphous silicon layer, a SiO.sub.2 layer, a C-doped SiO.sub.2 layer, a doped N-type amorphous silicon layer, a TCO conductive layer and an electrode are sequentially disposed on a front surface of the N-type crystalline silicon wafer. An intrinsic amorphous silicon layer, a SiO.sub.2 layer, a C-doped SiO.sub.2 layer, a doped P-type amorphous silicon layer, a TCO conductive layer and an electrode are sequentially disposed on a back surface of the N-type crystalline silicon wafer. The doped P-type amorphous silicon layer includes a lightly B-doped amorphous silicon layer and a heavily B-doped amorphous silicon layer.

A method for manufacturing a solar cell can include forming a tunnel layer on a back surface of a semiconductor substrate; forming an amorphous silicon layer on the tunnel layer; crystallizing the amorphous silicon layer into a crystalline silicon layer; performing a diffusion process to form a doped region in the crystalline silicon layer; forming an insulating layer on the crystalline silicon layer; and forming an electrode contacting with the crystalline silicon layer through an opening of the insulating layer.

A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.

A method of manufacturing a solar cell includes forming a photoelectric converter including an amorphous semiconductor layer, forming an electrode connected to the photoelectric converter, and performing a post-treatment by providing light to the photoelectric converter and the electrode, wherein, in the performing of the post-treatment, a plasma lighting system (PLS) is used as a light source, and a processing temperature is within a range from about 100 C. to about 300 C.

An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.

A method of manufacturing a solar cell can include forming a silicon oxide film on a semiconductor substrate and successively exposing the silicon oxide film to a temperature in a range of 570 C. to 700 C. to anneal the silicon oxide film.

Devices and methods for reducing optical losses in transparent conductive oxides (TCOs) used in silicon heterojunction (SHJ) solar cells while enhancing series resistance are disclosed herein. In particular, the methods include reducing the thickness of TCO layers by about 200% to 300% and depositing hydrogenated dielectric layers on top to form double layers of antireflection coating. It has been discovered that the conductivity of a thin TCO layer can be increased through a hydrogen treatment supplied from the capping dielectric during the post deposition annealing. The optimized cells with ITO/SiO.sub.x:H stacks achieved more than 41 mA/cm.sup.2 generation current on 120-micron-thick wafers while having approximately 100 Ohm/square sheet resistance. Further, solar cells and methods may include integration of ITO/SiO.sub.x:H stacks with Cu plating and use ITO/SiN.sub.x/SiO.sub.x triple layer antireflection coatings. The experimental data details the improved optics and resistance in cell stacks with varying materials and thicknesses.

A process for treating a stack intended for manufacture of a photovoltaic cell includes placing the stack in an enclosure, exposing the stack to electromagnetic radiation, and cooling the stack during exposure. The photovoltaic cell is cooled by injecting a gas flow into the enclosure, regulating the injected gas flow taking into account the temperature of the stack, and evacuating the gas flow from the enclosure taking into account the ambient temperature present in the enclosure.