Patent classifications
H01L33/28
LIGHT EMITTING DEVICE
A light emitting device including a first light emitting element and an optical member disposed over the first light emitting element. The optical member includes a light transmissive member and a ceramic component. The light transmissive member has a first upper surface, a second upper surface, and a lower surface opposing to the first upper surface and a second upper surface. The ceramic component is disposed on the second upper surface of the light transmissive member. The light transmissive member and the ceramic component each has a portion that overlaps with the first light emitting element when viewed in plan view.
Using a compliant layer to eliminate bump bonding
Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.
Using a compliant layer to eliminate bump bonding
Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.
METHOD FOR REMOVAL OF DEVICES USING A TRENCH
An epitaxial lateral overgrowth (ELO) layer is grown on an opening area of a substrate, wherein the ELO layer is higher than a surface 5 of a trench in the substrate. The trench is apt to form a symmetric shape of the ELO layer, which renders it suitable for flip-chip bonding The shape of the ELO layer has a depressed surface region at a back side of a bar formed by the ELO layer. A cleaving point is located higher than the bottom of the ELO layer, so that a force can be efficiently applied to 10 the cleaving point for removing the bar.
METHOD FOR REMOVAL OF DEVICES USING A TRENCH
An epitaxial lateral overgrowth (ELO) layer is grown on an opening area of a substrate, wherein the ELO layer is higher than a surface 5 of a trench in the substrate. The trench is apt to form a symmetric shape of the ELO layer, which renders it suitable for flip-chip bonding The shape of the ELO layer has a depressed surface region at a back side of a bar formed by the ELO layer. A cleaving point is located higher than the bottom of the ELO layer, so that a force can be efficiently applied to 10 the cleaving point for removing the bar.
Display panel, display device and fabricating method of display panel comprising carrier functional layer having molecular chanins formed by cross-linking under light irradiation
A display panel comprises includes: a base substrate; a first electrode layer and a second electrode layer on a side of the base substrate; a light-emitting layer between the first electrode layer and the second electrode layer; and a carrier functional layer located at least one of between the first electrode layer and the light-emitting layer, and between the second electrode layer and the light-emitting layer. The light-emitting layer has a plurality of light-emitting portions with different emergent light wavebands; and the carrier functional layer has a plurality of carrier functional portions corresponding to the plurality of light-emitting portions, the plurality of carrier functional portions having molecular chains, which is formed by cross-linking of monomers containing functional groups under light irradiation.
TUNABLE OPTICAL MICROCAVITY FOR MODULATION AND GENERATION OF SPECIFIC RADIATION
The present invention relates to a tuneable optical microcavity, characterised in that it comprises electrodes (12) on substrates (11), wherein the electrodes are comprised in the structure of dielectric or metal mirrors (13), or each of the electrodes has at least one dielectric or metal minor (13) on it, or the electrodes are semitransparent metal minors (13), wherein the mirrors are preferably located at a separation being a multiple of ½ lambda, where lambda is the central wavelength of the cavity mode, the cavity between the mirrors being filled with material (15) that changes the effective refractive index under the influence of external fields, preferably such as electric, magnetic field, thermal and mechanical stress.
Ultra-wideband, free space optical communication apparatus
Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a free space optical (FSO) communication apparatus includes a digital data port, an array of light-emitting diodes (LEDs) each configured to have a transient response time of less than 500 picoseconds (ps), and current drive circuitry coupled between the digital data port and the array of LEDs.
USING A COMPLIANT LAYER TO ELIMINATE BUMP BONDING
Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.
USING A COMPLIANT LAYER TO ELIMINATE BUMP BONDING
Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.