A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Systems and methods are provided for transferring a remote frequency identification (RFID) inlay from a first substrate to a second substrate. An RFID inlay is secured to a first substrate with a first adhesive. The RFID inlay is brought into the vicinity of a second substrate and secured to the second substrate with a second adhesive. The RFID inlay is then dissociated from the first substrate. The RFID inlay may be dissociated from the first substrate by softening the first adhesive, such as by the application of heat or the application of a softening substance. Alternatively, the RFID inlay may be dissociated from the first substrate without softening the first adhesive, but rather by differential release, whereby a release force is applied between the two substrates, with the release force being greater than the release strength of the first adhesive, but less than the release strength of the second adhesive.

Systems and methods are provided for transferring a remote frequency identification (RFID) inlay from a first substrate to a second substrate. An RFID inlay is secured to a first substrate with a first adhesive. The RFID inlay is brought into the vicinity of a second substrate and secured to the second substrate with a second adhesive. The RFID inlay is then dissociated from the first substrate. The RFID inlay may be dissociated from the first substrate by softening the first adhesive, such as by the application of heat or the application of a softening substance. Alternatively, the RFID inlay may be dissociated from the first substrate without softening the first adhesive, but rather by differential release, whereby a release force is applied between the two substrates, with the release force being greater than the release strength of the first adhesive, but less than the release strength of the second adhesive.

A sealing structure including: a set of base members forming a sealed space; a through-hole which is formed in at least one of the base members, and communicates with the sealed space; and a sealing member that seals the through-hole. An underlying metal film including a bulk-like metal such as gold is provided on a surface of the base member provided with the through-hole. The sealing member seals the through-hole while being bonded to the underlying metal film, and includes: a sealing material which is bonded to the underlying metal film, and includes a compressed product of a metal powder of gold or the like, the metal powder having a purity of 99.9% by mass or more; and a lid-like metal film which is bonded to the sealing material, and includes a bulk-like metal such as gold. Further, the sealing material includes: an outer periphery-side densified region being in contact with an underlying metal film; and a center-side porous region being in contact with the through-hole. The densified region has a porosity of 10% or less in terms of an area ratio at any cross-section.

An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.

A manufacturing method includes the step of forming a diced semiconductor wafer (10) including semiconductor chips (11) from a semiconductor wafer (W) typically on a dicing tape (T1). The diced semiconductor wafer (10) on the dicing tape (T1) is laminated with a sinter-bonding sheet (20). The semiconductor chips (11) each with a sinter-bonding material layer (21) derived from the sinter-bonding sheet (20) are picked up typically from the dicing tape (T1). The semiconductor chips (11) each with the sinter-bonding material layer are temporarily secured through the sinter-bonding material layer (21) to a substrate. Through a heating process, sintered layers are formed from the sinter-bonding material layers (21) lying between the temporarily secured semiconductor chips (11) and the substrate, to bond the semiconductor chips (11) to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to individual semiconductor chips while reducing loss of the sinter-bonding material.

A manufacturing method includes the step of forming a diced semiconductor wafer (10) including semiconductor chips (11) from a semiconductor wafer (W) typically on a dicing tape (T1). The diced semiconductor wafer (10) on the dicing tape (T1) is laminated with a sinter-bonding sheet (20). The semiconductor chips (11) each with a sinter-bonding material layer (21) derived from the sinter-bonding sheet (20) are picked up typically from the dicing tape (T1). The semiconductor chips (11) each with the sinter-bonding material layer are temporarily secured through the sinter-bonding material layer (21) to a substrate. Through a heating process, sintered layers are formed from the sinter-bonding material layers (21) lying between the temporarily secured semiconductor chips (11) and the substrate, to bond the semiconductor chips (11) to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to individual semiconductor chips while reducing loss of the sinter-bonding material.

The present invention discloses a assembling method, a manufacturing method, an device and an electronic apparatus of flip-die. The method for assembling a flip-die, comprises: temporarily bonding the flip-die onto a laser-transparent first substrate, wherein bumps of the flip-die are located on the side of the flip-die opposite to the first substrate; aligning the bumps with pads on a receiving substrate; irradiating the original substrate with laser from the first substrate side to lift-off the flip-die from the first substrate; and attaching the flip-die on the receiving substrate. A faster assembly rate can be achieved by using the present invention. A smaller chip size can be achieved by using the present invention. A lower profile can be achieved by using the present invention.