Manufacturing method for semiconductor device

Abstract

A manufacturing method includes the step of forming a diced semiconductor wafer (10) including semiconductor chips (11) from a semiconductor wafer (W) typically on a dicing tape (T1). The diced semiconductor wafer (10) on the dicing tape (T1) is laminated with a sinter-bonding sheet (20). The semiconductor chips (11) each with a sinter-bonding material layer (21) derived from the sinter-bonding sheet (20) are picked up typically from the dicing tape (T1). The semiconductor chips (11) each with the sinter-bonding material layer are temporarily secured through the sinter-bonding material layer (21) to a substrate. Through a heating process, sintered layers are formed from the sinter-bonding material layers (21) lying between the temporarily secured semiconductor chips (11) and the substrate, to bond the semiconductor chips (11) to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to individual semiconductor chips while reducing loss of the sinter-bonding material.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the steps of: dicing a semiconductor wafer being held on a dicing tape into a diced semiconductor wafer including a plurality of semiconductor chips; laminating a sinter-bonding sheet prepared by forming a coating including a binder component and sinterable particles containing a conductive metal onto a separator serving as a carrier or a substrate and drying the coating onto the diced semiconductor wafer on the dicing tape so that the sinter-bonding sheet exists opposite to the dicing tape, to transfer a sinter-bonding material layer derived from the sinter-bonding sheet to each of the semiconductor chips; picking up the semiconductor chips together with the sinter-bonding material layer adhering to each of the chips, to give semiconductor chips each with the sinter-bonding material layer; temporarily securing, to a substrate, the semiconductor chips each with the sinter-bonding material layer through the sinter-bonding material layer; and forming sintered layers, through a heating process, from the sinter-bonding material layers lying between the semiconductor chips and the substrate which are temporarily secured to each other, to bond the semiconductor chips to the substrate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the diced semiconductor wafer is formed in the dicing step by blade dicing of the semiconductor wafer.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising, between the dicing step and the lamination step, the step of temporarily expanding the dicing tape which holds the diced semiconductor wafer.

4. The method for manufacturing a semiconductor device according to claim 1, further comprising, between the lamination step and the picking-up step, the step of temporarily expanding the dicing tape which holds the diced semiconductor wafer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the diced semiconductor wafer is formed in the dicing step by: forming embrittled regions in the semiconductor wafer being held on the dicing tape, where the embrittled regions will serve to cleave the wafer into semiconductor chips; and expanding the dicing tape which holds the semiconductor wafer, to cleave the semiconductor wafer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the picking-up step comprises picking up the semiconductor chips each with the sinter-bonding material layer from the dicing tape.

7. The method for manufacturing a semiconductor device according to claim 1, further comprising, between the lamination step and the picking-up step, the step of laminating a wafer processing tape onto the sinter-bonding sheet in the diced semiconductor wafer with the sinter-bonding sheet, and removing the dicing tape from the diced semiconductor wafer, wherein the picking-up step comprises picking up the semiconductor chips each with the sinter-bonding material layer from the wafer processing tape.

8. The method for manufacturing a semiconductor device according to claim 4, further comprising, between the expanding step and the picking-up step, the step of laminating a wafer processing tape onto the sinter-bonding material layer adhering to each of the semiconductor chips in the diced semiconductor wafer, and removing the dicing tape from the diced semiconductor wafer, where the sinter-bonding material layer is derived from the sinter-bonding sheet, wherein the picking-up step comprises picking up the semiconductor chips each with the sinter-bonding material layer from the wafer processing tape.

9. A method for manufacturing a semiconductor device, the method comprising the steps of: forming embrittled regions in a semiconductor wafer being held on a dicing tape, where the embrittled regions will serve to cleave the wafer into a plurality of semiconductor chips; laminating a sinter-bonding sheet prepared by forming a coating including a binder component and sinterable particles containing a conductive metal onto a separator serving as a carrier or substrate and drying the coating onto the semiconductor wafer on the dicing tape so that the sinter-bonding sheet exists opposite to the dicing tape; cleaving the semiconductor wafer together with the sinter-bonding sheet by expanding the dicing tape which holds the semiconductor wafer, to form a diced semiconductor wafer including the plurality of semiconductor chips each adhering to a sinter-bonding material layer derived from the sinter-bonding sheet; picking up the semiconductor chips together with the sinter-bonding material layer adhering to each of the chips, to give semiconductor chips each with the sinter-bonding material layer; temporarily securing, to a substrate, the semiconductor chips each with the sinter-bonding material layer through the sinter-bonding material layer; and forming, through a heating process, sintered layers from the sinter-bonding material layers lying between the semiconductor chips and the substrate which are temporarily secured to each other, to bond the semiconductor chips to the substrate.

10. A method for manufacturing a semiconductor device, the method comprising the steps of: laminating a sinter-bonding sheet prepared by forming a coating including a binder component and sinterable particles containing a conductive metal onto a separator serving as a carrier or substrate and drying the coating onto a semiconductor wafer being held on a dicing tape so that the sinter-bonding sheet exists opposite to the dicing tape; singularizing the semiconductor wafer on the dicing tape together with the sinter-bonding sheet to form a diced semiconductor wafer including a plurality of semiconductor chips each adhering to a sinter-bonding material layer derived from the sinter-bonding sheet; picking up the semiconductor chips together with the sinter-bonding material layer adhering to the chips, to give semiconductor chips each with the sinter-bonding material layer; temporarily securing, to a substrate, the semiconductor chips each with the sinter-bonding material layer through the sinter-bonding material layer; and forming, through a heating process, sintered layers from the sinter-bonding material layers lying between the semiconductor chips and the substrate which are temporarily secured to each other, to bond the semiconductor chips to the substrate.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the diced semiconductor wafer is formed in the singularization step by blade dicing of the semiconductor wafer and the sinter-bonding sheet lying on the wafer.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the diced semiconductor wafer is formed in the singularization step by: forming embrittled regions in the semiconductor wafer being held on the dicing tape, where the embrittled regions will serve to cleave the wafer into semiconductor chips; and subsequently expanding the dicing tape which holds the semiconductor wafer, to cleave the semiconductor wafer and the sinter-bonding sheet lying on the wafer.

13. The method for manufacturing a semiconductor device according to claim 9, wherein the picking-up step comprises picking up the semiconductor chips each with the sinter-bonding material layer from the dicing tape.

14. The method for manufacturing a semiconductor device according to claim 9, further comprising, before the picking-up step, the step of laminating a wafer processing tape onto the sinter-bonding material layer adhering to each of the semiconductor chips in the diced semiconductor wafer, where the sinter-bonding material layer is derived from the sinter-bonding sheet, and removing the dicing tape from the diced semiconductor wafer, wherein the picking-up step comprises picking up the semiconductor chips each with the sinter-bonding material layer from the wafer processing tape.

15. The method for manufacturing a semiconductor device according to claim 1, wherein the sintered layers each have a thickness of from 60% to 140% of an average thickness of the sintered layers.

16. The method for manufacturing a semiconductor device according to claim 1, wherein the sintered layers have an average thickness of 5 to 200 μm.

17. The method for manufacturing a semiconductor device according to claim 1, wherein the sinterable particles comprise at least one selected from the group consisting of silver, copper, silver oxide, and copper oxide.

18. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a power semiconductor device.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIGS. 1(a)-1(d) illustrates some steps in a semiconductor device manufacturing method according to one embodiment of the present invention;

(2) FIG. 2 illustrates a step subsequent to the steps illustrated in FIGS. 1(a)-1(d);

(3) FIGS. 3(a)-3(b) illustrates steps subsequent to the step illustrated in FIG. 2;

(4) FIGS. 4(a)-4(b) illustrates steps subsequent to the steps illustrated in FIGS. 3(a)-3(b);

(5) FIGs. 5(a)-5(b) illustrates some steps in a semiconductor device manufacturing method according to one embodiment of the present invention;

(6) FIGS. 6(a)-6(c) illustrates some steps in a semiconductor device manufacturing method according to one embodiment of the present invention;

(7) FIGS. 7(a)-7(c) illustrates some steps in a semiconductor device manufacturing method according to one embodiment of the present invention;

(8) FIGS. 8(a)-8(d) illustrates some steps in a semiconductor device manufacturing method according to one embodiment of the present invention;

(9) FIGS. 9(a)-9(b) illustrates some steps in a semiconductor device manufacturing method according to one embodiment of the present invention;

(10) FIGS. 10(a)-10(c) illustrates steps subsequent to the steps illustrated in FIGS. 9(a)-9(b);

(11) FIGS. 11(a)-11(d) illustrates some steps in a semiconductor device manufacturing method according to one embodiment of the present invention;

(12) FIGS. 12(a)-12(b) illustrates some steps in a semiconductor device manufacturing method according to one embodiment of the present invention; and

(13) FIGS. 13(a)-13(d) illustrates some steps in a semiconductor device manufacturing method according to one embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

(14) FIGS. 1(a) to 4(b) illustrate a semiconductor device manufacturing method according to one embodiment of the present invention. The semiconductor device manufacturing method according to the embodiment is a method for manufacturing a power semiconductor device or another semiconductor device including semiconductor chips in sinter-bonded areas. The method includes a dicing step, a lamination step, a picking-up step, a temporary securing step, and a sinter bonding step as follows.

(15) In the dicing step, a semiconductor wafer W, which is held on a dicing tape T1, receives blade dicing to form a diced semiconductor wafer 10, as illustrated in FIGS. 1(a) and 1(b).

(16) The dicing tape T1 typically has a multilayer structure including a substrate (carrier) and a pressure-sensitive adhesive layer and has an adhesive face T1a, which is defined by the pressure-sensitive adhesive layer, on one side. The semiconductor wafer W has an element-formed side on which semiconductor elements are built, and a backside opposite to the element-formed side. The backside bears plane electrodes (not shown) as external electrodes. Non-limiting examples of a material to constitute the wafer body of the semiconductor wafer W include silicon carbide (SiC), gallium nitride (GaN), and other semiconductor materials for power semiconductor devices. The semiconductor wafer W has a thickness of typically 20 to 1000 μm.

(17) Specifically in the step, initially, the adhesive face T1a of the dicing tape T1 adheres to the element-formed side (the lower side in the figure) of the semiconductor wafer W. A ring frame R is applied to the periphery of the adhesive face T1a of the dicing tape T1. The ring frame R is a member with which a conveying mechanism, such as a conveying arm, of a dicer (dicing saw) (not shown) is in contact upon conveying of the work, while the ring frame R is adhering to the dicing tape T1.

(18) In the step, next, a rotary blade (not shown) of a dicer is driven while the semiconductor wafer W is held on the adhesive face T1a of the dicing tape T1. Thus, cutting of the semiconductor wafer W proceeds. The cutting proceeds along intended cutting lines while running water is continuously fed toward the rotary blade and the semiconductor wafer W. In FIG. 1(b), cutting grooves G formed using the dicing rotary blade are schematically indicated by thick lines. The cutting grooves G may reach the inside of the dicing tape T1. Through the dicing step as above, dicing (singularization) of the semiconductor wafer W into chips operates, to form a diced semiconductor wafer 10 including semiconductor chips 11, on the dicing tape T1. The diced semiconductor wafer 10 formed by the above procedure has a spacing between the semiconductor chips 11 of typically 10 to 500 μm.

(19) In the embodiment, next, the diced semiconductor wafer 10 is laminated with a sinter-bonding sheet 20 (lamination step), as illustrated in FIG. 1(c). The sinter-bonding sheet 20 is a sheet of a composition including a binder component and sinterable particles containing a conductive metal. The sheet is laminated onto the surface or the backside of the diced semiconductor wafer 10 on the dicing tape T1, so that the sheet exists opposite to the dicing tape T1. A non-limiting example of the pressing means for lamination is a pressure roller. The lamination operates at a temperature of typically from room temperature to 200° C. under a load of typically 0.01 to 10 MPa. The step enables batchwise transfer of the sinter-bonding material layer 21 to each of the semiconductor chips 11 in the diced semiconductor wafer 10, by compression bonding of the sinter-bonding material derived from the sinter-bonding sheet 20.

(20) The sinter-bonding sheet 20 is used for sinter bonding between targets to be bonded, and is a sheet of a composition including a binder component and sinterable particles containing a conductive metal, as described above.

(21) The sinterable particles in the sinter-bonding sheet 20 are particles that contain a conductive metal element and are sinterable. Non-limiting examples of the conductive metal element include gold, silver, copper, palladium, tin, and nickel. Non-limiting examples of a material to constitute the sinterable particles as above include gold, silver, copper, palladium, tin, and nickel; and alloys of two or more different metals selected from the group consisting of these metals. Non-limiting examples of a material to constitute the sinterable particles also include metal oxides such as silver oxide, copper oxide, palladium oxide, and tin oxide. The sinterable particles may also be particles having a core-shell structure. For example, the sinterable particles may be core-shell structure particles, which include a core mainly containing copper, and a shell mainly containing, for example, gold or silver and covering the core. In the embodiment, the sinterable particles preferably include at least one selected from the group consisting of silver particles, copper particles, silver oxide particles, and copper oxide particles. The sinterable particles are preferably selected from silver particles and copper particles, from the viewpoint of actually providing high electric conductivity and high thermal conductivity in the formed sintered layers. In addition, silver particles are easily handleable and are preferred from the viewpoint of oxidation resistance. For example, assume that a sintering process operates in sinter bonding of semiconductor chips to a silver-plated copper substrate, using a sintering material including copper particles as the sinterable particles. This sintering process has to be performed in an inert environment such as a nitrogen atmosphere. However, a sintering process in sinter bonding using a sintering material including silver particles as the sinterable particles can operate appropriately even in an air atmosphere.

(22) The sinterable particles for use herein have an average particle diameter (average particle size) of preferably 2000 nm or less, more preferably 800 nm or less, and still more preferably 500 nm or less, from the viewpoint typically of actually providing a low sintering temperature of the sinterable particles, to surely provide satisfactory sinterability. The sinterable particles have an average particle diameter of preferably 1 nm or more, more preferably 10 nm or more, still more preferably 50 nm or more, and still more preferably 100 nm or more, from the viewpoint of allowing the sinterable particles to be satisfactorily dispersible in the sinter-bonding sheet 20 or in the composition to form the sheet 10. The average particle diameter of the sinterable particles can be measured by observation using a scanning electron microscope (SEM).

(23) The sinter-bonding sheet 20 contains the sinterable particles in a proportion of preferably 60 to 99 mass percent, more preferably 65 to 98 mass percent, still more preferably 70 to 97 mass percent, and still more preferably 70 to 95 mass percent, from the viewpoint of actually providing highly reliable sinter bonding.

(24) In the embodiment, the binder component in the sinter-bonding sheet 20 includes a thermally decomposable polymer binder and a low-boiling binder and may further include one or more other components such as a plasticizer. The thermally decomposable polymer binder is a binder component that is decomposable in a high-temperature heating process for sinter bonding, and is an element that contributes to a retained sheet form of the sinter-bonding sheet 20 before the heating process. In the embodiment, the thermally decomposable polymer binder is a material that is solid at normal temperature (23° C.), from the viewpoint of surely providing sheet form retainability. Non-limiting examples of such thermally decomposable polymer binders include polycarbonate resins and acrylic resins.

(25) Examples of the polycarbonate resins for use as the thermally decomposable polymer binder include aliphatic polycarbonates whose backbone is composed of an aliphatic chain and does not include, between carbonic acid ester groups (—O—CO—O—) in the backbone, benzene rings and other moieties derived from aromatic compounds; and aromatic polycarbonates which include a moiety derived from an aromatic compound between carbonic acid ester groups (—O—CO—O—) in the backbone. Non-limiting examples of the aliphatic polycarbonates include poly(ethylene carbonate)s and poly(propylene carbonate)s. Non-limiting examples of the aromatic polycarbonates include polycarbonates including a bisphenol-A structure in the backbone.

(26) Examples of the acrylic resins for use as the thermally decomposable polymer binder include polymers of an acrylic ester and/or a methacrylic ester each having C.sub.4-C.sub.18 linear or branched alkyl. Hereinafter the term “(meth)acrylic” indicates “acrylic” and/or “methacrylic”; and the term “(meth)acrylate” indicates “acrylate” and/or “methacrylate”. Non-limiting examples of the alkyl moiety of the (meth)acrylic ester to form the acrylic resin as the thermally decomposable polymer binder include methyl, ethyl, propyl, isopropyl, n-butyl, t-butyl, isobutyl, amyl, isoamyl, hexyl, heptyl, cyclohexyl, 2-ethylhexyl, octyl, isooctyl, nonyl, isononyl, decyl, isodecyl, undecyl, lauryl, tridecyl, tetradecyl, stearyl, and octadecyl.

(27) The acrylic resin as the thermally decomposable polymer binder may also be a polymer further including a monomer unit derived from a monomer other than the (meth)acrylic esters. Examples of such other monomers include carboxy-containing monomers, acid anhydride monomers, hydroxy-containing monomers, sulfo-containing monomers, and phosphate-containing monomers. Specifically, non-limiting examples of the carboxy-containing monomers include acrylic acid, methacrylic acid, carboxyethyl acrylate, carboxypentyl acrylate, itaconic acid, maleic acid, fumaric acid, and crotonic acid. Examples of the acid anhydride monomers include, but are not limited to, maleic anhydride and itaconic anhydride. Non-limiting examples of the hydroxy-containing monomers include 2-hydroxyethyl (meth)acrylate, 2-hydroxypropyl (meth) acrylate, 4-hydroxybutyl (meth)acrylate, 6-hydroxyhexyl (meth)acrylate, 8-hydroxyoctyl (meth)acrylate, 10-hydroxydecyl (meth)acrylate, 12-hydroxylauryl (meth)acrylate, and 4-(hydroxymethyl) cyclohexylmethyl (meth) acrylate. Non-limiting examples of the sulfo-containing monomers include styrenesulfonic acid, allylsulfonic acid, 2-(meth)acrylamido-2-methylpropanesulfonic acid, (meth) acrylamidopropanesulfonic acid, sulfopropyl (meth)acrylate, and (meth)acryloyloxynaphthalenesulfonic acid. A non-limiting example of the phosphate-containing monomers is 2-hydroxyethylacryloyl phosphate.

(28) The thermally decomposable polymer binder has a weight-average molecular weight of preferably 10000 or more. The “weight-average molecular weight” of the thermally decomposable polymer binder herein refers to a value measured by gel permeation chromatography (GPC) and calibrated with a polystyrene standard.

(29) The sinter-bonding sheet 20 may contain the thermally decomposable polymer binder in a proportion of preferably 0.5 to 10 mass percent, more preferably 0.8 to 8 mass percent, and still more preferably 1 to 6 mass percent, from the viewpoint of appropriately exhibiting the function of sheet form retaining.

(30) The “low-boiling binder” in the sinter-bonding sheet 20 refers to a binder that has a viscosity of 1×10.sup.5 Pa.Math.s or less and is liquid or semi-liquid at 23° C., where the viscosity is measured using a dynamic viscoelastometer (trade name HAAKE MARS III, supplied by Thermo Fisher Scientfic). The viscosity measurement operates using 20-mm diameter parallel plates as fixtures at a plate-to-plate gap of 100 μm and a shear rate in rotary shearing of 1 s.sup.−1.

(31) Non-limiting examples of the low-boiling binder include terpene alcohols, alcohols other than terpene alcohols, alkylene glycol alkyl ethers, and ethers other than alkylene glycol alkyl ethers. Non-limiting examples of the terpene alcohols include isobornylcyclohexanol, citronellol, geraniol, nerol, carveol, and α-terpineol. Non-limiting examples of the alcohols other than terpene alcohols include pentanol, hexanol, heptanol, octanol, 1-decanol, ethylene glycol, diethylene glycol, propylene glycol, butylene glycol, and 2,4-diethyl-1,5-pentanediol. Examples of the alkylene glycol alkyl ethers include ethylene glycol butyl ether, diethylene glycol methyl ether, diethylene glycol ethyl ether, diethylene glycol butyl ether, diethylene glycol isobutyl ether, diethylene glycol hexyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol dibutyl ether, diethylene glycol butyl methyl ether, diethylene glycol isopropyl methyl ether, triethylene glycol methyl ether, triethylene glycol dimethyl ether, triethylene glycol butyl methyl ether, propylene glycol propyl ether, dipropylene glycol methyl ether, dipropylene glycol ethyl ether, dipropylene glycol propyl ether, dipropylene glycol butyl ether, dipropylene glycol dimethyl ether, tripropylene glycol methyl ether, and tripropylene glycol dimethyl ether. Non-limiting examples of the ethers other than alkylene glycol alkyl ethers include ethylene glycol ethyl ether acetate, ethylene glycol butyl ether acetate, diethylene glycol ethyl ether acetate, diethylene glycol butyl ether acetate, and dipropylene glycol methyl ether acetate. The sinter-bonding sheet 20 may include each of different low-boiling binders alone or in combination. The low-boiling binder(s) in the sinter-bonding sheet 20 is preferably selected from terpene alcohols and is more preferably isobornylcyclohexanol, from the viewpoint of providing stability at normal temperature (room temperature).

(32) The sinter-bonding sheet 20 has a thickness at 23° C. of preferably 5 μm or more, more preferably 10 μm or more, and preferably 300 μm or less, and more preferably 150 μm or less. The sinter-bonding sheet 20 or the sinter-bonding composition to form the sheet 20 has a viscosity at 70° C. of typically 5×10.sup.3 to 1×10.sup.7 Pa.Math.s, and preferably 1×10.sup.4 to 1×10.sup.6 Pa.Math.s.

(33) The sinter-bonding sheet 20 can be prepared typically by blending the components in a solvent (vehicle) to give a varnish, applying the varnish onto a separator serving as a carrier or substrate, to form a coating, and drying the coating. Non-limiting examples of the solvent usable for the preparation of the varnish include organic solvents and alcohol solvents.

(34) After the lamination step, the method according to the embodiment performs a reversing step as illustrated in FIG. 1(d). Specifically, in the step, a wafer processing tape T2 having an adhesive face T2a adheres to the work, and the dicing tape T1 is removed from the work, where the work is the diced semiconductor wafer 10 with the sinter-bonding sheet 20. The adhesive face T2a of the wafer processing tape T2 has an adhesive strength equal to or greater than the adhesive strength of the adhesive face T1a of the processing tape T1. In the step, for example, the adhesive face T2a of the wafer processing tape T2 adheres to the sinter-bonding sheet 20 in the diced semiconductor wafer 10 with the sinter-bonding sheet 20, and then the dicing tape T1 is removed from the diced semiconductor wafer 10.

(35) In the semiconductor device manufacturing method according to the embodiment, next, each of the semiconductor chips 11 together with the sinter-bonding material layer 21 adhering tightly to each chip is picked up from the wafer processing tape T2 to give a sinter-bonding material layer-associated semiconductor chip 11 (picking-up step), as illustrated in FIG. 2. Specifically, in the step, a target sinter-bonding material layer-associated semiconductor chip 11 to be picked up is plunged up through the wafer processing tape T2 by elevating a pin lifter 33 of a picking-up mechanism from below the wafer processing tape T2 in the figure, and the semiconductor chip 11 is sucked and held by a suction collet C. The sinter-bonding material layer-associated semiconductor chips 11 can be picked up using the sucking-holding action of the suction collet C as above. This is also applied to the after-mentioned picking-up step.

(36) Next, each sinter-bonding material layer-associated semiconductor chip 11 is temporarily secured, by compression bonding, through the sinter-bonding material layer 21 to a supporting substrate S (temporary securing step), as illustrated in FIG. 3(a). Specifically, each sinter-bonding material layer-associated semiconductor chip 11 is pressed and thereby temporarily secured through the sinter-bonding material layer 21 to the supporting substrate S, typically using a chip mounter. Non-limiting examples of the supporting substrate S include lead frames; and insulated substrates with wiring such as copper wiring. On the supporting substrate S, the chip may be mounted on the base material (matrix) such as a copper wiring or lead frame, or may be mounted on a plated film disposed on the base material. Non-limiting examples of the plated film include gold-plated films, silver-plated films, nickel-plated films, palladium-plated films, and platinum-plated films. In the step, the temporary securing operates at a temperature of typically from room temperature to 300° C. by pressing under a load of typically 0.01 to 50 MPa for a bonding time of typically 0.01 to 300 seconds.

(37) Next, with reference to FIG. 3(b), the work receives a heating process to allow the sinter-bonding material layers 21 to convert into sintered layers 22, where the sinter-bonding material layers 22 lie between the semiconductor chips 11 and the supporting substrate S, which are temporarily secured to each other. This allows the semiconductor chips 11 to be sinter-bonded to the supporting substrate S (sinter bonding step). Specifically, the work undergoes a predetermined high-temperature heating process, and this causes, in the sinter-bonding material layers 21 lying between the supporting substrate S and the semiconductor chips 11, the low-boiling binder to volatilize, causes the thermally decomposable polymer binder to thermally decompose and volatilize, and causes the conductive metal in the sinterable particles to sinter. This forms the sintered layers 22 between the supporting substrate S and the semiconductor chips 11 and allows the semiconductor chips 11 to bond to the supporting substrate S while establishing and keeping electrical connection with the supporting substrate S. The sinter bonding in the step operates at a temperature of typically from 150° C. to 400° C., and preferably from 250° C. to 350° C., at a pressure of typically 60 MPa or less, and preferably 40 MPa or less, for a bonding time of typically 0.3 to 300 minutes, and preferably 0.5 to 240 minutes. Typically within these condition ranges, the temperature profile and the pressure profile for performing the sinter bonding step are appropriately determined. The sinter bonding step as above can operate using an apparatus that perform heating and pressurization simultaneously. Non-limiting examples of such an apparatus include flip-chip bonders and parallel plate pressing machines. The step is preferably performed in a nitrogen atmosphere, or under reduced pressure, or in a reducing gas atmosphere, to prevent or minimize oxidation of the metal or metals involved in sinter bonding.

(38) In the embodiment, the sintered layers 22 formed in the sinter bonding step each have a thickness in the range of preferably from 60% to 140%, more preferably from 80% to 120%, and still more preferably from 90% to 110%, of the average thickness of the sintered layer 22. With increasing uniformity in thicknesses of the sintered layers 22, the sintered layers 22 can more readily have high bonding reliability. The sintered layers 22 have an average thickness of preferably 5 to 200 μm, and more preferably 10 to 150 μm. This configuration is preferred for relaxing the internal stress in the sintered layers 22 caused by heat stress, to surely have sufficient thermal-shock reliability and for reducing not only the sinter bonding cost, but also the semiconductor device production cost.

(39) The semiconductor device manufacturing method according to the embodiment then performs a wire bonding step. In the step, a terminal area (not shown) of each semiconductor chip 11 and a terminal area (not shown) of the supporting substrate S are electrically connected (coupled) to each other, where necessary via a bonding wire W, as illustrated in FIG. 4(a). The connection between the bonding wire W and the terminal area of the semiconductor chip 11 or the terminal area of the supporting substrate S is provided typically through ultrasonic welding with heating. Non-limiting examples of the bonding wire W usable herein include gold wires, aluminum wires, and copper wires. The wire bonding operates at a wire heating temperature of typically 80° C. to 250° C., and preferably 80° C. to 220° C., for a heating time of from several seconds to several minutes.

(40) Next, a resinous encapsulant M is formed to protect the semiconductor chips 11 and the bonding wires W on the substrate S (encapsulation step), as illustrated in FIG. 4(b). In this step, the resinous encapsulant M is disposed or formed by the transfer molding technology using dies. The resinous encapsulant M may be made typically from an epoxy resin. The heating to form the resinous encapsulant M in the step operates at a temperature typically from 165° C. to 185° C. for a time typically from 60 seconds to several minutes. The resinous encapsulant M, when not sufficiently cured in the encapsulation step, subsequently undergoes a postcure step to be fully cured.

(41) Thus, a semiconductor device including semiconductor chips in sinter-bonded areas can be manufactured.

(42) The semiconductor device manufacturing method according to the embodiment may perform a picking-up step and a subsequent reversing step as follows, instead of the reversing step described above with reference to FIG. 1(d) and the picking-up step described above with reference to FIG. 2.

(43) After the lamination step described above with reference to FIG. 1(c), namely, after the step of laminating the sinter-bonding sheet 20 onto the diced semiconductor wafer 10 on the dicing tape T1, a target semiconductor chip 11 together with the sinter-bonding material layer 21 in intimate contact with the chip is picked up from the dicing tape T1 to give a sinter-bonding material layer-associated semiconductor chip 11 (picking-up step), as illustrated in FIG. 5(a). In this picking-up step, a suction collet C is used to hold the semiconductor chip 11 by the suction action upon the sinter-bonding material layer 21 of the sinter-bonding material layer-associated semiconductor chip 11. Next, the suction collet C, which has picked-up the sinter-bonding material layer-associated semiconductor chip 11, transfers the semiconductor chip 11 to another suction collet C′ (reversing step), as illustrated in FIG. 5(b). The suction collet C′ holds the semiconductor chip 11 by the suction action upon the chip-mounting side in the sinter-bonding material layer-associated semiconductor chip 11. The resulting sinter-bonding material layer-associated semiconductor chip 11 will undergo a temporary securing step as described above with reference to FIG. 3(a).

(44) The semiconductor device manufacturing method according to the embodiment may preform an expanding step between the dicing step described above with reference to FIGS. 1(a) and 1(b) and the lamination step described above with reference to FIG. 1(c). In the expanding step, the dicing tape T1, which holds the diced semiconductor wafer 10, is temporarily expanded, as illustrated in FIGS. 6(a)-6(c).

(45) The expanding step employs an expander. Initially, as illustrated in FIG. 6(a), the dicing tape T1 bearing the diced semiconductor wafer 10 and a ring frame R on the adhesive face T1a is secured to a holder 31 of the expander. Next, as illustrated in FIG. 6(b), a hollow cylindrical plunger 32 of the expander ascends while coming in contact with the dicing tape T1 from below. This expands the dicing tape T1, on which the diced semiconductor wafer 10 is laminated, so as to allow the dicing tape T1 to elongate in two-dimensional directions including the radial direction and the circumferential direction of the diced semiconductor wafer 10. The expanding operates at a temperature of typically −20° C. to 70° C. Then, the plunger 32 descends to release the dicing tape T1 from the expanded state, as illustrated in FIG. 6(c). After the expansion, a portion outside of the region in which the diced semiconductor wafer is held in the dicing tape T1 may shrink by heating. The heating operates at a temperature of typically 100° C. to 300° C. This configuration is preferred for restraining the separation distance between the semiconductor chips 11 from narrowing after the expansion.

(46) The semiconductor device manufacturing method according to the embodiment may perform an expanding step as illustrated in FIGS. 7(a)-7(c), between the lamination step described above with reference to FIG. 1(c) and the reversing step described above with reference to FIG. 1(d). When the method employs the step described above with reference to FIGS. 5(a)-5(b), the method may perform the expanding step as illustrated in FIGS. 7(a)-7(c) between the lamination step described above with reference to FIG. 1(c) and the picking-up step described above with reference to FIG. 5(a).

(47) This expanding step employs an expander. Initially, as illustrated in FIG. 7(a), the dicing tape T1 bearing the diced semiconductor wafer 10 with the sinter-bonding sheet 20 and a ring frame R on the adhesive face T1a is secured to a holder 31 of the expander. Next, as illustrated in FIG. 7(b), a hollow cylindrical plunger 32 of the expander ascends while coming in contact with the dicing tape T1 from below. This expands the dicing tape T1, on which the diced semiconductor wafer 10 is laminated, so as to allow the dicing tape T1 to elongate in two-dimensional directions including the radial direction and the circumferential direction of the diced semiconductor wafer 10. The expanding operates at a temperature of typically −20° C. to 70° C. Then, the plunger 32 descends to release the dicing tape T1 from the expanded state, as illustrated in FIG. 7(c). After the expansion, a portion outside of the region of the dicing tape T1 in which the diced semiconductor wafer is held may shrink by heating. The heating operates at a temperature of typically 100° C. to 300° C. This configuration is preferred for restraining the separation distance between the semiconductor chips 11 from narrowing after the expansion. The expanding step as above can surely provide sufficient separation distance between the pick-up target semiconductor chips 11 before the picking-up step and therefore enables the picking-up step to operate appropriately.

(48) The semiconductor device manufacturing method according to the embodiment may perform a dicing step as illustrated in FIGS. 8(a)-8(d), instead of the dicing step described above with reference to FIGS. 1(a) and 1(b).

(49) In this dicing step, initially, the semiconductor wafer W being held on the dicing tape T1 undergoes stealth dicing, to form embrittled regions (weakened regions) F in the semiconductor wafer W, where the embrittled regions F contribute to cleaving of the wafer into semiconductor chips, as illustrated in FIG. 8(a).

(50) In the stealth dicing, laser light, whose collecting spot is focused on the inside of the semiconductor wafer W, is applied to the semiconductor wafer W along intended dicing lines typically from the side opposite to the dicing tape T1. Thus, the embrittled regions F are formed in the semiconductor wafer W due to ablation by multiphoton absorption. Such a technique for forming embrittled regions F in a semiconductor wafer on intended dicing lines by laser irradiation is described in detail typically in JP-A No. 2002-192370. In the embodiment, laser irradiation conditions may be adjusted as appropriate typically within the following condition ranges.

(51) Laser Irradiation Conditions

(52) (A) Laser Light

(53) Laser source: diode-pumped Nd:YAG laser Wavelength: 1064 nm Laser spot cross-sectional area: 3.14×10.sup.−8 cm.sup.2 Laser form: Q switched pulse Pulse rate: 100 kHz or less Pulse duration: 1 μs or shorter Output: 1 mJ or less Laser quality: TEM00 Polarization property: linear polarization
(B) Condenser Lens Magnifying power: 100× or less Numerical aperture (NA): 0.55 Transmittance relative to laser light wavelength: 100% or less
(C) Traveling Speed of the Table on which the Semiconductor Substrate is placed: 280 mm/sec or Less

(54) Before or after the stealth dicing as above, the semiconductor wafer W may be thinned by grinding on the backside of the wafer. The semiconductor wafer W, which has undergone the stealth dicing, is in such a state as to be cleaved along the embrittled regions F by expansion of the dicing tape T1 which holds the wafer.

(55) In this dicing step, next, the dicing tape T1 bearing the semiconductor wafer W after the stealth dicing and a ring frame R on the adhesive face T1a is secured to a holder 31 of an expander, as illustrated in FIG. 8(b). Next, the dicing tape T1 holding the semiconductor wafer W after the stealth dicing is temporarily expanded, to cleave the semiconductor wafer W, as illustrated in FIGS. 8(c) and 8(d). Specifically, initially, a hollow cylindrical plunger 32 of the expander ascends while coming in contact with the dicing tape T1 from below. This allows the dicing tape T1 on which the semiconductor wafer W is laminated to elongate in two-dimensional directions including the radial direction and the circumferential direction of the semiconductor wafer W, as illustrated in FIG. 8(c). The expansion operates at a temperature of typically from −20° C. to 70° C. The expansion as above causes cracking in the embrittled regions F in the semiconductor wafer W, to dice the semiconductor wafer W into semiconductor chips 11. Then, the plunger 32 descends to release the dicing tape T1 from the expanded state, as illustrated in FIG. 8(d). After the expansion, a portion outside of the region of the dicing tape T1 in which the diced semiconductor wafer is held may shrink by heating. The heating operates at a temperature of typically 100° C. to 300° C. This configuration is preferred for restraining the separation distance between the semiconductor chips 11 from narrowing after the expansion.

(56) The dicing step as above can also provide the diced semiconductor wafer 10 on the dicing tape T1. The semiconductor chips 11 in the diced semiconductor wafer 10 exist with spacing of typically 10 to 500 μm. The formed diced semiconductor wafer 10 will undergo the lamination step described above with reference to FIG. 1(c).

(57) In the lamination step described above with reference to FIG. 1(c) in the semiconductor device manufacturing method as described above, the sinter-bonding sheet 20 for supplying the sinter-bonding material is laminated onto the diced semiconductor wafer 10 (including the semiconductor chips 11 after singularization) on the dicing tape T1. This configuration is suitable for efficient batchwise supply of the sinter-bonding material to each of the semiconductor chips 11, namely, suitable for efficient batchwise transfer and formation of the sinter-bonding material layer 21 onto each of the semiconductor chips 11.

(58) In addition, in the semiconductor device manufacturing method according to the embodiment, the diced semiconductor wafer 10 (namely, the semiconductor wafer W after singularization into chips while being held on the dicing tape T1) formed on the dicing tape T1 in the dicing step has a spacing between chips of typically 10 to 500 μm, as described above. The spacing between chips is smaller typically than the semiconductor chip thickness and is short. In the lamination step, the sinter-bonding sheet 20 is laminated onto the diced semiconductor wafer 10 as above (namely, the sinter-bonding sheet 20 is not laminated onto semiconductor chips with relatively large clearance (spacing) between them, which chips have been singularized from a semiconductor wafer W and then arranged on a predetermined processing tape). Consequently, the semiconductor device manufacturing method according to the embodiment is suitable for reducing loss of a sinter-bonding material in batchwise supply of the sinter-bonding material to each of the semiconductor chips 11.

(59) As described above, the semiconductor device manufacturing method according to the embodiment is suitable for efficiently supplying the sinter-bonding material to each semiconductor chip 11 while reducing loss of the sinter-bonding material.

(60) FIGS. 9 and 10 illustrate a semiconductor device manufacturing method according to one embodiment of the present invention. The semiconductor device manufacturing method according to the embodiment is a manufacturing method for a power semiconductor device or another semiconductor device including semiconductor chips in sinter-bonded areas. The method includes a stealth dicing step, a lamination step, a cleaving step, a picking-up step, a temporary securing step, and a sinter bonding step as follows.

(61) In the stealth dicing step, initially, a semiconductor wafer W being held on a dicing tape T1 undergoes stealth dicing, to form embrittled regions F in the semiconductor wafer W, as illustrated in FIG. 9(a), where the embrittled regions F will serve to cleave the wafer into semiconductor chips. Before or after the stealth dicing as above, the semiconductor wafer W may be thinned by grinding on its backside (in the embodiment, the upper side in the figure). The semiconductor wafer W after the stealth dicing is in such a state as to be cleavable along the embrittled regions F by the expansion of the dicing tape T1. Specific embodiments and conditions of the stealth dicing on the semiconductor wafer W are as described above with reference to FIG. 8(a).

(62) In the embodiment, next, the sinter-bonding sheet 20 is laminated onto the semiconductor wafer W (lamination step), as illustrated in FIG. 9(b). The sinter-bonding sheet 20 is a sheet of a composition including a conductive metal-containing sinterable particles and a binder component, as described above. The sinter-bonding sheet 20 is laminated onto the surface or the backside of the semiconductor wafer W on the dicing tape T1, so that the sheet exists opposite to the dicing tape T1. A non-limiting example of the pressing means or device for lamination is a pressure roller. The lamination operates at a temperature of typically from room temperature to 200° C. under a load of typically from 0.01 to 10 MPa. The step enables efficient batchwise supply of the sinter-bonding material to individual portions of the semiconductor wafer W to be singularized (diced) into semiconductor chips, namely, efficient batchwise transfer and formation of the sinter-bonding material layer onto individual portions of the semiconductor wafer W to be singularized into semiconductor chips.

(63) Next, the method performs the cleaving step as illustrated in FIGS. 10(a)-(c). The step employs an expander. Initially, the dicing tape T1 bearing the semiconductor wafer W with the sinter-bonding sheet 20 and a ring frame R on the adhesive face T1a is secured to a holder 31 of the expander, as illustrated in FIG. 10(a). Next, a hollow cylindrical plunger 32 of the expander ascends while coming in contact with the dicing tape T1 from below to expand the dicing tape T1 on which the semiconductor wafer W is laminated, so as to elongate the dicing tape T1 in two-dimensional directions including the radial direction and the circumferential direction of the semiconductor wafer W, as illustrated in FIG. 10(b). The expansion operates at a temperature of typically from −20° C. to 70° C. The expansion as above causes cracking of the semiconductor wafer W in the embrittled regions F, and the semiconductor wafer W is diced into semiconductor chips 11. Then the plunger 32 descends to release the dicing tape T1 from the expanded state, as illustrated in FIG. 10(c). As described above, the cleaving step temporarily expands the dicing tape T1 holding the semiconductor wafer W, and thereby cleaves the semiconductor wafer W together with the overlying sinter-bonding sheet 20. This can form a diced semiconductor wafer 10 which includes semiconductor chips 11 each adhering to a sinter-bonding material layer 21 derived from the sinter-bonding sheet 20. After the expansion, a portion of the dicing tape T1 outside the region in which the diced semiconductor wafer is held may shrink by heating. The heating operates at a temperature of typically 100° C. to 300° C. This configuration is preferred for restraining the separation distance between the semiconductor chips 11 from narrowing after the expansion.

(64) After the cleaving step, the method according to the embodiment performs the reversing step described above with reference to FIG. 1(d); the picking-up step described above with reference to FIG. 2; the temporary securing step described above with reference to FIG. 3(a); the sinter bonding step described above with reference to FIG. 3(b); the wire bonding step described above with reference to FIG. 4(a); and the encapsulation step described above with reference to FIG. 4(b), each of which steps has been described relating to the other embodiment. The method may perform the picking-up step described above with reference to FIG. 5(a) and the reversing step described above with reference to FIG. 5(b), instead of the reversing step described above with reference to FIG. 1(d) and the picking-up step described above with reference to FIG. 2, each of which steps has been described relating to the other embodiment.

(65) A semiconductor device including semiconductor chips in sinter-bonded areas can be produced by the above procedure.

(66) In the lamination step described above with reference to FIG. 9(b) in the semiconductor device manufacturing method according to the embodiment, the sinter-bonding sheet 20 for supplying the sinter-bonding material is laminated onto the semiconductor wafer W after stealth dicing on the dicing tape T1. The configuration as above is suitable for efficient batchwise supply of the sinter-bonding material to individual portions of the semiconductor wafer W which will be singularized (diced) into semiconductor chips, namely, efficient batchwise transfer and formation of the sinter-bonding material layer 21 onto individual portions of the semiconductor wafer W which will be singularized into semiconductor chips.

(67) In addition, in the lamination step in the embodiment, the sinter-bonding sheet 20 is laminated on a semiconductor wafer W which has not undergone singularization into chips (namely, semiconductor wafer W without chip-to-chip clearance). The lamination step as above enables compression bonding of the sinter-bonding sheet 20 for supplying the sinter-bonding material to the semiconductor wafer W in entire regions for the sheet to be laminated on the wafer. Accordingly, the semiconductor device manufacturing method according to the embodiment is suitable for reducing loss of the sinter-bonding material fed to the semiconductor chips 11 obtained in course of the process.

(68) As described above, the semiconductor device manufacturing method according to the embodiment is suitable for efficiently supplying the sinter-bonding material to each of the semiconductor chips 11 while reducing loss of the sinter-bonding material.

(69) FIGS. 11(a)-11(d) illustrates some steps of a semiconductor device manufacturing method according to one embodiment of the present invention. The semiconductor device manufacturing method according to the embodiment is a manufacturing method for a power semiconductor device or another semiconductor device including semiconductor chips in sinter-bonded areas. The method includes a lamination step, a singularization step, a picking-up step, a temporary securing step, and a sinter bonding step as follows.

(70) In the lamination step, a sinter-bonding sheet 20 is laminated onto a semiconductor wafer W being held on an adhesive face T1a of a dicing tape T1, as illustrated in FIGS. 11(a) and 11(b). The sinter-bonding sheet 20 is a sheet of a composition including a binder component and conductive metal-containing sinterable particles, as described above. The sinter-bonding sheet 20 is laminated onto the surface or the backside of the semiconductor wafer W on the dicing tape T1 so that the sheet exists opposite to the dicing tape T1. A non-limiting example of the pressing means or device for lamination is a pressure roller. The lamination operates at a temperature typically from room temperature to 200° C. under a load of typically 0.01 to 10 MPa. The step enables efficient batchwise supply of the sinter-bonding material to individual portions of the semiconductor wafer W which will be singularized (diced) into semiconductor chips, namely, efficient batchwise transfer and formation of the sinter-bonding material layer onto individual portions of the semiconductor wafer W which will be singularized into semiconductor chips. Before the step, the semiconductor wafer W may be thinned by grinding on the backside (in the embodiment, the upper side in the figure).

(71) Next, the method performs the singularization step as illustrated in FIG. 11(c). Specifically, a rotary blade (not shown) of a dicer is driven while the semiconductor wafer W with the sinter-bonding sheet 20 is held on the adhesive face T1a of the dicing tape T1. Thus, cutting of the semiconductor wafer W and the sinter-bonding sheet 20 lying on the wafer W proceeds. The cutting proceeds along intended cutting lines, while running water is continuously fed toward the rotary blade and the semiconductor wafer W. In FIG. 11(c), cutting grooves G formed using the dicing rotary blade are schematically indicated by thick lines. The cutting grooves G may reach the inside of the dicing tape T1. Through the singularization step as above, a diced semiconductor wafer 10 is formed on the dicing tape T1, where the diced semiconductor water 10 includes semiconductor chips 11 adhering to a sinter-bonding material layer 21 derived from the sinter-bonding sheet 20.

(72) In the embodiment, the method performs the reversing step as illustrated in FIG. 11(d) after the lamination step. Specifically, in the step, a wafer processing tape T2 having an adhesive face T2a is laminated on the work, and the dicing tape T1 is removed from the work, where the work is the diced semiconductor wafer 10 with the sinter-bonding sheet 20. The adhesive face T2a of the processing tape T2 has an adhesive strength equal to or higher than the adhesive strength of the adhesive face T1a of the processing tape T1. In the step, for example, the adhesive face T2a of the wafer processing tape T2 adheres to the sinter-bonding sheet 20 in the diced semiconductor wafer 10 with the sinter-bonding sheet 20, and then the dicing tape T1 is removed from the diced semiconductor wafer 10.

(73) After the singularization step, the method according to the embodiment performs the picking-up step described above with reference to FIG. 2; the temporary securing step described above with reference to FIG. 3(a); the sinter bonding step described above with reference to FIG. 3(b); the wire bonding step described above with reference to FIG. 4(a); and the encapsulation step described above with reference to FIG. 4(b), each of which steps has been described relating to the other embodiment.

(74) In the embodiment, the method may preform a picking-up step and a subsequent reversing step as follows, instead of the reversing step described above with reference to FIG. 11(d) and the picking-up step described above with reference to FIG. 2.

(75) After the singularization step described above with reference to FIG. 11(c), a target semiconductor chip 11 together with the sinter-bonding material layer 21 adhering to the chip is picked up from the dicing tape T1 to give a sinter-bonding material layer-associated semiconductor chip 11, as illustrated in FIG. 12(a) (picking-up step). In this picking-up step, a suction collet C is used to hold the semiconductor chip 11 by the sucking action upon the sinter-bonding material layer 21 side of the sinter-bonding material layer-associated semiconductor chip 11. Next, the suction collet C, which has picked up the sinter-bonding material layer-associated semiconductor chip 11, transfers the semiconductor chip 11 to another suction collet C′, as illustrated in FIG. 12(b) (reversing step). The suction collet C′ holds the semiconductor chip 11 by the sucking action upon the chip side of the sinter-bonding material layer-associated semiconductor chip 11. The sinter-bonding material layer-associated semiconductor chip 11 will undergo the temporary securing step as described above with reference to FIG. 3(a).

(76) In the embodiment, the method may perform a singularization step through stealth dicing as follows, instead of the singularization step through blade dicing described above with reference to FIG. 11(c).

(77) Initially, the semiconductor wafer W being held on the dicing tape T1 receives stealth dicing, to form embrittled regions F in the semiconductor wafer W as illustrated in FIG. 13(a), where the embrittled regions F will serve to cleave the wafer into semiconductor chips. The semiconductor wafer W after stealth dicing is in such a state as to be cleavable along the embrittled regions F by the expansion of the dicing tape T1 which holds the wafer. Specific embodiments and conditions for the stealth dicing on the semiconductor wafer W are as described above with reference to FIG. 8(a).

(78) Next, the dicing tape T1 bearing the semiconductor wafer W with the sinter-bonding sheet 20 and a ring frame R on the adhesive face T1a is secured to a holder 31 of an expander, as illustrated in FIG. 13(b). Next, a hollow cylindrical plunger 32 of the expander ascends while coming in contact with the dicing tape T1 from below, to expand the dicing tape T1, on which the semiconductor wafer W is laminated, so as to elongate the dicing tape T1 in two-dimensional directions including the radial direction and the circumferential direction of the semiconductor wafer W, as illustrated in FIG. 13(c). The expansion operates at a temperature of typically from −20° C. to 70° C. The expansion as above causes cracking in the embrittled regions F in the semiconductor wafer W and thereby causes the wafer W to be singularized (diced) into semiconductor chips 11. Then, the plunger 32 descends to release the dicing tape T1 from the expanded state, as illustrated in FIG. 13(d). As described above, in this singularization step, the dicing tape T1 holding the semiconductor wafer W is temporarily expanded. This cleaves the semiconductor wafer W together with the overlying sinter-bonding sheet 20 and enables formation of a diced semiconductor wafer 10 including the semiconductor chips 11 each adhering to a sinter-bonding material layer 21 derived from the sinter-bonding sheet 20. After the expansion, a portion in the dicing tape T1 outside the region in which the diced semiconductor wafer is held may shrink by heating. The heating operates at a temperature of typically from 100° C. to 300° C. This configuration is preferred for restraining the separation distance between the semiconductor chips 11 from narrowing after the expansion.

(79) A semiconductor device including semiconductor chips in sinter-bonded areas can be manufactured by the procedure as above.

(80) The semiconductor device manufacturing method according to the embodiment performs the lamination step described above with reference to FIG. 11(b) so as to laminate the sinter-bonding sheet 20 onto the semiconductor wafer W on the dicing tape T1 as described above, where the sinter-bonding sheet 20 will serve to supply the sinter-bonding material. The configuration as above is suitable for efficient batchwise supply of the sinter-bonding material to individual portions of the semiconductor wafer W to be singularized (diced) into semiconductor chips 11, namely, for efficient batchwise transfer and formation of the sinter-bonding material layer to the portions in the semiconductor wafer W to be singularized into semiconductor chips.

(81) In addition, in the lamination step of the semiconductor device manufacturing method according to the embodiment, the sinter-bonding sheet 20 is laminated onto the semiconductor wafer W which has not undergone singularization into chips (namely, semiconductor wafer W without chip-to-chip clearance). The lamination step as above allows the sinter-bonding sheet 20 for supplying the sinter-bonding material to bond to the semiconductor wafer W through compression bonding in entire regions to be laminated with the wafer. Consequently, the semiconductor device manufacturing method according to the embodiment is suitable for reducing loss of the sinter-bonding material to be fed to the semiconductor chips 11 obtained through the process.

(82) As described above, the semiconductor device manufacturing method according to the embodiment is suitable for efficiently supplying the sinter-bonding material to each of the semiconductor chips 11 while reducing loss of the sinter-bonding material.

(83) W semiconductor wafer

(84) G cutting groove

(85) F embrittled regions

(86) 10 diced semiconductor wafer

(87) 11 semiconductor chip

(88) 20 sinter-bonding sheet

(89) 21 sinter-bonding material layer

(90) 22 sintered layer

(91) T1 dicing tape

(92) T2 wafer processing tape

(93) S supporting substrate (substrate)