A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.

A semiconductor package includes a first substrate, a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate, a first molding part surrounding the first semiconductor chip and the passive device on the first substrate, a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device, a second molding part surrounding the second semiconductor chip on the first molding part, first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connect the first substrate to the second semiconductor chip, and external terminals provided under the first substrate.

A semiconductor package includes a lower semiconductor chip disposed on a lower redistribution substrate, lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip, conductive structures disposed on the lower redistribution substrate, a lower molding layer disposed on the lower redistribution substrate and covering a top surface of the lower semiconductor chip, an upper redistribution substrate disposed on the lower molding layer and electrically connected to the conductive structures, an upper semiconductor chip disposed on the upper redistribution substrate, upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip, and an upper molding layer disposed on the upper redistribution substrate and covering a sidewall of the upper semiconductor chip. The number of the conductive structures is greater than that of chip pads of the upper semiconductor chip.

An antenna apparatus in a packaged electronic device includes: an antenna assembly with a conductive antenna, and an insulator; a conductive feed line extending on or in a substrate; a conductive layer with an aperture on or in the substrate between the conductive feed line and an exposed portion of the conductive antenna; and a support structure mounted to a portion of the substrate and to a portion of the antenna assembly to support the antenna assembly and to provide an air gap between the exposed portion of the conductive antenna and the aperture.

A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, a RDL structure, an underfill layer, a protection layer, and a cap. The TIV is aside the die. The encapsulant laterally encapsulates the die and the TIV. The RDL structure is electrically connected to the die. The underfill layer is disposed between the die and the RDL structure and laterally encapsulated by the encapsulant. The protection layer is overlying the die and the encapsulant. The cap covers a top surface of the TIV and laterally aside the protection layer. A top surface of the cap is higher than a top surface of the encapsulant and lower than a top surface of the protection layer.

Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

A method for removing a resist layer is provided. A resist layer is formed with a material comprising a metal oxide core with organic ligands. A chlorine-containing compound or a methyl group-containing compound is globally applied onto the resist layer to allow the chlorine-containing compound or the methyl group-containing compound to perform a ligand exchange process with the resist layer so as to remove the resist layer through sublimation.

A semiconductor package structure is provided. The semiconductor package structure includes a lead frame and passive component. The lead frame includes a paddle and a plurality of leads. The lead frame includes a first surface and a second surface opposite to the first surface. The passive component includes an external connector. A pattern of the external connector is corresponding to a pattern of the plurality of leads of the lead frame.

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.