A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

The present disclosure is directed to a package that includes openings that extend into the package. The openings are filled with a conductive material to electrically couple a first die in the package to a second die in the package. The conductive material that fills the openings forms electrical interconnection bridges between the first die and the second die. The openings in the package may be formed using a laser and a non-doped molding compound, a doped molding compound, or a combination of doped or non-doped molding compounds.

The present disclosure is directed to a package that includes openings that extend into the package. The openings are filled with a conductive material to electrically couple a first die in the package to a second die in the package. The conductive material that fills the openings forms electrical interconnection bridges between the first die and the second die. The openings in the package may be formed using a laser and a non-doped molding compound, a doped molding compound, or a combination of doped or non-doped molding compounds.

Semiconductor device package assemblies and associated methods are disclosed herein. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having a first metallization structure at the front side; (2) a semiconductor device package having a first side, a second side with a recess, and a second metallization structure at the first side and a contacting region exposed in the recess at the second side; (3) an interconnect structure at least partially positioned in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another.

Semiconductor device package assemblies and associated methods are disclosed herein. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having a first metallization structure at the front side; (2) a semiconductor device package having a first side, a second side with a recess, and a second metallization structure at the first side and a contacting region exposed in the recess at the second side; (3) an interconnect structure at least partially positioned in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another.

A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.

A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.

A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.