An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processer, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processer is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processer. The buffer device is disposed on the data processer. The thermally conductive shield covers the data processer, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processer.

A three-dimensional (3D) memory device includes a peripheral device, a plurality of memory strings, a layer between the peripheral device and the plurality of memory strings, and a contact. The layer includes a conduction region and an isolation region. The contact extends through the isolation region of the layer.

A three-dimensional (3D) memory device includes a peripheral device, a plurality of memory strings, a layer between the peripheral device and the plurality of memory strings, and a contact. The layer includes a conduction region and an isolation region. The contact extends through the isolation region of the layer.

Provided is a semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between at least two substrates among the plurality of substrates have an electrode junction structure in which electrodes on the respective bonding surfaces are in direct contact with each other. The electrode junction structure is for electrical connection between the two substrates. In at least one of the two substrates, at least one of the electrode constituting the electrode junction structure or a via for connection of the electrode to a wiring line in the multi-layered wiring layer has a structure in which a protective film for prevention of diffusion of an electrically-conductive material constituting the electrode and the via is inside the electrically-conductive material.

Provided is a semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between at least two substrates among the plurality of substrates have an electrode junction structure in which electrodes on the respective bonding surfaces are in direct contact with each other. The electrode junction structure is for electrical connection between the two substrates. In at least one of the two substrates, at least one of the electrode constituting the electrode junction structure or a via for connection of the electrode to a wiring line in the multi-layered wiring layer has a structure in which a protective film for prevention of diffusion of an electrically-conductive material constituting the electrode and the via is inside the electrically-conductive material.

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

The invention relates to a modular element (2) comprising a stratification of first and second electroconductive plates (PH2, PB2) which are separated by an intermediate dielectric layer (CD2) and at least one electronic power switching chip (CP1, CP2) which is implanted between the first and second plates, the chip having a upper face comprising a first power electrode and a switching control electrode and a lower face comprising a second power electrode, and the first and second power electrodes being in electrical continuity respectively with the first and second plates. According to the invention, the modular element comprises a plurality of openings (OG2, OA2, OB2, OC2, OD2) extending into the stratification from outer surfaces of the first and second plates and perpendicularly to said outer surfaces, the plurality of openings comprising at least one first opening (OG2) communicating with the switching control electrode and at least one second opening (OA2, OB2) passing through the entire stratification, the first and second openings each comprising a dielectric layer (DE2) and an electroconductive layer (CI2), and the electroconductive layer of the first opening being electrically connected to the switching control electrode.

The invention relates to a modular element (2) comprising a stratification of first and second electroconductive plates (PH2, PB2) which are separated by an intermediate dielectric layer (CD2) and at least one electronic power switching chip (CP1, CP2) which is implanted between the first and second plates, the chip having a upper face comprising a first power electrode and a switching control electrode and a lower face comprising a second power electrode, and the first and second power electrodes being in electrical continuity respectively with the first and second plates. According to the invention, the modular element comprises a plurality of openings (OG2, OA2, OB2, OC2, OD2) extending into the stratification from outer surfaces of the first and second plates and perpendicularly to said outer surfaces, the plurality of openings comprising at least one first opening (OG2) communicating with the switching control electrode and at least one second opening (OA2, OB2) passing through the entire stratification, the first and second openings each comprising a dielectric layer (DE2) and an electroconductive layer (CI2), and the electroconductive layer of the first opening being electrically connected to the switching control electrode.