Patent classifications
H01L2224/04
BONDED SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME
A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.
POWER SEMICONDUCTOR MODULE
Provided is a power semiconductor module including: a metal base plate; an insulating substrate arranged on the metal base plate and provided with an electrode; a semiconductor element arranged on the insulating substrate; a case arranged on the metal base plate so as to surround the insulating substrate and the semiconductor element; and a potting material filled into a space defined by the metal base plate and the case so as to encapsulate the insulating substrate and the semiconductor element. The potting material includes: a silicone gel; and a conductivity-imparting agent that is added to the gel and contains a silicon atom and an ionic group.
POWER SEMICONDUCTOR MODULE
Provided is a power semiconductor module including: a metal base plate; an insulating substrate arranged on the metal base plate and provided with an electrode; a semiconductor element arranged on the insulating substrate; a case arranged on the metal base plate so as to surround the insulating substrate and the semiconductor element; and a potting material filled into a space defined by the metal base plate and the case so as to encapsulate the insulating substrate and the semiconductor element. The potting material includes: a silicone gel; and a conductivity-imparting agent that is added to the gel and contains a silicon atom and an ionic group.
METHOD FOR PRODUCING STRUCTURE, AND STRUCTURE
This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion
METHOD FOR PRODUCING STRUCTURE, AND STRUCTURE
This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion
METHOD TO FORM A 3D SEMICONDUCTOR DEVICE AND STRUCTURE
A method to form a 3D semiconductor device, the method including: providing a first wafer including first circuits including transistors and interconnection; preparing a second wafer including a silicon layer; performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer including non-silicon atoms, forming second circuits over the second wafer, the second circuits including transistors and interconnection; transferring and then bonding the second wafer on top of the first wafer; and then thinning the second wafer to a thickness of less than ten microns.
METHOD TO FORM A 3D SEMICONDUCTOR DEVICE AND STRUCTURE
A method to form a 3D semiconductor device, the method including: providing a first wafer including first circuits including transistors and interconnection; preparing a second wafer including a silicon layer; performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer including non-silicon atoms, forming second circuits over the second wafer, the second circuits including transistors and interconnection; transferring and then bonding the second wafer on top of the first wafer; and then thinning the second wafer to a thickness of less than ten microns.
APPARATUS FOR BONDING SUBSTRATES AND METHOD OF BONDING SUBSTRATES
A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.
APPARATUS FOR BONDING SUBSTRATES AND METHOD OF BONDING SUBSTRATES
A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.
LAYER STRUCTURES FOR MAKING DIRECT METAL-TO-METAL BONDS AT LOW TEMPERATURES IN MICROELECTRONICS
Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150 C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.